pe_macro(1)
The test starts by testing the ability to perform the AND1 function between
the following sources and destinations:
SRC
Destination
Message Reference
Each flag bit
lsb
Message #1–#40
Each flag bit
lflag
Message #41–#80
Each flag bit
cflag
Message #81–#120
Each flag bit
vflag
Message #121–#160
Each flag bit
zflag
Message #161–#200
Each flag bit
nflag
Message #201–#240
Each flag bit
tflag
Message #241–#180
Each flag bit
fflag
Message #281–#320
Each flag bit
rflag
Message #321–#360
Each flag bit
64[c0]
Message #361–#400
If it detects an error in the result, it prints an error message giving the
instruction under test, the source and destination operands, the expected
result and the actual result.
After each AND1 operation, it tests the lflag. If this is wrong, it prints an
error message giving the expected and actual value of the flag.
Next, initializing the destinations as shown, the test performs the AND1
function between the following source and destination operands.
Dest
Init.
SRC
Destination
Message Reference
1
1025[c2]
Each flag bit
Message #401–#422
1
Each flag bit
Each PReg bit
Message #423–#444
0
1025[c2]
Each flag bit
Message #445–#466
0
Each flag bit
Each PReg bit
Message #467–#488
After each AND1 operation, it tests the lflag. If this is wrong, it prints an
error message giving the expected and actual value of the flag.
If it detects an error in the result, it prints an error message giving the
instruction under test, the destination operand, the expected result and the
actual result.
•
AndTests1
: Register To Register AND Test (8, 16, 32 and 64 bit) — This test
performs 8-bit, 16-bit, 32-bit, and 64-bit AND operations.
After each AND, if it detects an error, the test prints an error message which
gives the AND the test was attempting, the expected answer and the actual
answer.
After each AND, it checks the flag bits. If any of these is in error, an error
message is printed giving the operation attempted, the expected flag bits and
the actual flag bits. The flag bits are collected as shown:
B–18 Data Parallel Unit Reference Pages
