pe_macro(1)
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mtest0
: LOAD/STORE Overlap Test — The purpose of this test is to
verify the ability to perform overlapping operations by overlapping store,
multiplication and load operations. It is possible for the multiplication
process to corrupt the load and store data; but it is much more likely that the
process of loading and storing data upsets the multiplication process.
This test sets the e-bit and m-bit on all PEs. It then performs the following
operations in succession:
Each PE stores test data into 8 different PMem locations
Each PE performs five 64-bit multiplications
Each PE loads test data from the 8 different PMem locations
Checks test data
Checks multiplication data
If an error occurs, the test prints an error message which gives the attempted
operation, the expected result and the actual result.
•
mtest1
: Dispatcher Lock And M-Bit Queue Test — Performs these tests:
Test #1 (Message #1–#2) — Tests the m-bit queue and dispatcher lock,
and verifies that the m-bits are correctly set and cleared.
First, it uses MOV1UC to clear all m-bits and verifies that they are all
cleared. In rapid succession, it issues 32 commands to clear the m-bits,
and then a command to set the m-bits. It checks that the m-bits are
set. If there is a fault in the queue mechanism or dispatcher lock, the
command to set the m-bit may be lost.
Test #2 (Message #3–#5) — Tests the action of the m-bits. It verifies that
turning on the m-bits allows a store, that turning off the m-bits prevents
a store and that turning off the m-bits prevents a load.
Test #3 (Message #6) — Dispatcher lock test; tests to see if, with the
m-bit queue full, the dispatcher lock prevents subsequent commands from
overflowing the queue. It verifies not merely that the m-bits are correctly
set or cleared, but that they are functional at the proper time.
With all m-bits on, the test stores and loads data. In rapid succession it
issues 32 commands to clear the m-bits (filling up the queue), then sets
the m-bits and attempts to load the data originally stored. It verifies that
it receives the correct data.
If an error occurs, the test prints an error message which describes the
suspected failure.
•
mtest2
: Indirect LOAD/STORE Tests — This test verifies the ability of the
PEs to store and load indirectly addressed data to and from 0x1000 locations
in PMem.
The test enables all the PEs for load/store operations, and gives each PE
unique data to store and load. Using indirect addressing, it stores data at
0x1000 PMem locations, incrementing the data for each location. Still using
indirect addressing, it reads back the data from all those PMem locations and
verifies the accuracy of the data. Finally, using direct addressing, it reads
back the data from all those PMem locations and again verifies its accuracy.
Finally, the test has all PEs invert the bits in their original data and repeat
the above test.
B–32 Data Parallel Unit Reference Pages
