DM16E1 / DM4E1 Operation and Installation Manual - 204-4001-19
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+ At the digital interface, CT109 reflects aggregate status, remaining OFF whenever the aggregate is in an
error condition.
5.3. V.35 / V.36/V.11 Selection Straps
To use the digital interface with V.35 DTEs, straps E16 to E24 must be set to position 0-2. For V.36/V.11
interfaces, straps E16 to E24 must be set to position 0-1. Factory configuration is position 0-2.
The straps are located on the aggregate cards. The cards must be removed to allow access to the straps.
Figure 13. Location of V.35 / V.36/V.11 interface straps
5.4. Digital interface signals
CT103 (DT) is the data signal supplied by the DTE (the MUX will always be considered as the DCE). If
CT106 is off, a marker signal will be transmitted to the aggregate.
CT104 is the data signal supplied to the DTE. If CT109 is off, a marker signal will be transmitted to the
DTE.
CT105 is a control signal generated by the DTE, indicating a request to transmit. It can be configured to be
observed or ignored (forced to on).
CT106 is a control signal generated by the equipment, indicating that the MUX is ready to transmit. In the
MUX, CT106 follows CT105, unless a test that alters its behavior is run.
CT107 is a control signal generated by the equipment, indicating that it is ready to operate. It remains
active in normal functioning, except when the BERT sequence is activated.
CT108 is a control signal generated by the DTE, indicating that the terminal is ready (DTR). It can be
configured to be observed or ignored (forced to on).
CT109 is a control signal generated by the equipment, indicating that it is detecting the aggregate carrier
signal and that the receiver is synchronized. In case of failure in the aggregate, CT109 remains off, and
CT104 is locked to the marker signal.
CT113 is the transmission clock supplied by the DTE. The MUX can be configured to use this signal in the
acquisition of CT103 data. In the absence of clock signal, CT113 will be keyed to the receiver clock, and
an alarm will be generated. It can be configured to be observed or ignored.
CT114 is the transmission clock used by the interface, being synchronized to the MUX transmission clock
or to the clock supplied by the DTE (CT113).
CT115 is the reception clock recovered from the aggregate (remote side).
CT128 is the external clock for data reception at the digital interface. When CT104 is enabled, it will be
synchronized to this clock. In the absence of clock signal at the interface, CT115 will be used as CT104
clock, and an alarm will be generated.
5.5. BERT
The digital interface can generate a BERT test pattern. The pattern for this card is 511 (29-1).
This test allows a quick verification of transmission quality without the need for external test equipment.
Error insertion is also possible.
The figure below shows the test pattern generation at this interface.
