AN201
Rev 1.5 | 87/91
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16.3.6 PORTC<7:0>
PC7~PC0 can be configured as the following functional port:
GPIO
RFDIN, the data input in the RF pass-through mode (for PC0 only)
SCLK, the the serial clock of the RF part SPI (for PC2 only)
CSB, the chip selection of RF part SPI (for PC3 only)
SDIO, the serial data of RF part SPI (for PC4 only)
Comparator input ( for PC0 and PC1 only, however it is not available since the ports are used to control the RF part)
Comparator output (for PC4 only, however it is not available since the port are used to control the RF part)
The internal circuit architecture of the port is shown in the below figure.
D
CLK
Q
Q
_
1
0
C2OUT
C2OUT Enable
D
CLK
Q
Q
_
RD
PORTC
RD
TRISC
WR
TRISC
WR
PORTC
Data
Bus
VDD
(Only PC4)
Analog Input
mode
To Comparator
(Only PC0 & PC1)
Figure 33. PC7~PC0 Architecture
