AN201
Rev 1.5 | 53/91
www.cmostek.com
Table 82. UCFG0 Bit Function Description
UCFG1, PROM address 0x2001
Table 83. UCFG1 Configuration Register
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
UCFG1
-
-
TSEL
FCMEN
IESO
RD_CTRL
LVREN <1:0>
Table 84. UCFG1 Bit Function Description
Bit
Name
Function
6
CPB
1 = disable Flash content protection
0 = enable Flash content protection. It can be read by the MCU and series ports cannot read it.
Notes:
The bit can only be rewritten from 1 to 0, but it cannot be rewritten from 0 to 1. The only way to
rewrite from 0 to 1 is to erase the registers including USER_OPT, then CPB will become1 after it
powers up again.
5
MCLRE
1 = PA5/MCLR pin executes the MCLR function, which is a reset pin.
0 = PA5/MCLR pin executes the PA5 function, which is a digital input pin.
4
PWRTEB
1 = disable PWRT
0 = enable PWRT
3
WDTE
1 = enable WDT, the program cannot disable it.
0 = disable WDT, but the program can enable WDT by setting the SWDTEN bit of the WDTCON
2:0
FOSC<2:0>
000 = 32 k crystal oscillator mode. The PA6/PA7 connects the low frequency crystal oscillator.
001 = 20 MHz crystal oscillator mode. The PA6/PA7 connects the high speed crystal oscillator.
010 = external clock mode, the PA6 is an IO pin, the PA7 connects to the clock input.
011 = INTOSC mode. The PA6 outputs the system clock divided by 2. The PA7 is an IO pin.
1xx = INTOSCIO mode, both the PA6 and PA7 are IO pins
Bit
Name
Function
5
TSEL
Instruction cycle selection bit.
1 = the instruction cycle duration is 2T
0 = the instruction cycle duration is 4T
4
FCMEN
Clock fault monitoring enabling bit.
1 = enable the clock fault monitoring
0 = disable the clock fault monitoring
3
IESO
2-speed clock enabling bit.
1 = enable
0 = disable
2
RD_CTRL
Port read control bit in output mode
1 = read the value of the PAD returned from the data port
0 = read the value of the Latch returned from the data port
