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16.3.3 PORTA4/PA4

PA4 can be configured as the following functional port:



GPIO

The internal circuit architecture of the port is shown in the below figure.

CLK

TRISA

WPUA

Data

Bus

VDD

CLK

WPUA

PORTA

/RAPU

VDD

TRISA

PORTA

CLK

IOCA

Interrupt

On Change

PORTA

ATEST0 EN

IR MODE

IR DATA

IR MODE

Figure 31. PA4 Architecture

Notes:

ATEST0 and IR are used for internal test, but not for users. Users can ignore them.

Summary of Contents for NextGenRF CMT2189B

Page 1: ...sting of transmitters receivers transceiver etc The product models covered in this document are shown in the table below Table 1 Product Models Covered in This Document Product Model Frequency Range M...

Page 2: ...t Configuration 24 2 7 9 Pause Interval Configuration 25 2 7 10 Tcycle Configuration 25 2 8 State and Function Register 27 2 8 1 Soft Reset 27 2 8 2 Operating State and State Switching 27 2 8 3 Operat...

Page 3: ...1 32 INDF and FSR Register 55 5 System Clock Source 56 5 1 Clock Source Mode 56 5 2 External Clock Mode 57 5 2 1 EC Mode 57 5 2 2 LP and XT Modes 57 5 3 Internal Clock Mode 57 5 3 1 Frequency Selectio...

Page 4: ...4 Interrupt Mode 78 14 1 INT Interrupt 78 14 2 PORTA Level Change Interrupt 79 14 3 Interrupt Response 79 14 4 Context Saving During Interrupts 81 15 MCU Sleep Mode for Energy Saving 81 15 1 Wakeup Mo...

Page 5: ...4 PC4 PC6 PA7 DIN 3 SPI PC0 PC 3 1 Figure 1 CMT2189B System Architecture The chip adopts the PLL PA architecture to achieve the Sub GHz wireless transmission function with supports of FIFO packet mode...

Page 6: ...pport of IOC and configurable pull up 11 PA2 T0CKI INT C1OUT Digital IO PA2 General purpose IO with support of IOC and configurable pull up T0CKI Timer 0 clock source input Max 4MHz INT External inter...

Page 7: ...rnal pull up resistor Notes 1 The MCU has 2 built in comparators but the 2 internal comparators cannot be used due to the pin packaging limitation and the multiplexing of RF part for some pins However...

Page 8: ...lator Upon power up the chip controls data transmission through the internal PC1 SDIO to fulfill data transmission at the corresponding frequency In this mode the frequency multiplier factor is fixed...

Page 9: ...power supply voltage to save power and prolong battery life In this mode the chip internal MCU can have the RF mode control by operating registers through the 3 wire SPI PC3 CSB PC2 SCLK PC1 SDIO to f...

Page 10: ...SB is pulled down and a R W bit is sent followed by a 7 bit register address After the chip selection enabling PC3 CSB is pulled down it is necessary to wait for at least half a PC2 SCLK cycle to star...

Page 11: ...olling RFCTRL to a high impedance input since the pull up inside RFCTRL can pull the level high Do not set the MCU pin to low output since pull down will consume power 2 5 RF Configuration Parameter W...

Page 12: ...egisters described below and then click Export to generate an exp file with file content as follows CMT2157B Configuration File Generated by CMOSTEK RFPDK 1 46 2017 11 14 13 47 Among them the annotati...

Page 13: ...her 8 bit of each 16 bit Word is an odd number address and the lower 8 bit is an even address The conversion of 24 Words gets 48 register configuration values with an address range of 0x00 0x2E the la...

Page 14: ...x60 0xC0A0 0x20 0xA0 0x21 0xC0 0x0000 0x22 0x00 0x23 0x00 0x0100 0x24 0x00 0x25 0x01 0x027C 0x26 0x7C 0x27 0x02 0x957B 0x28 0x7B 0x29 0x95 0x70F0 0x2A 0xF0 0x2B 0x70 0x0083 0x2C 0x83 0x2D 0x00 0x0000...

Page 15: ...ble to the hardware packet Tx mode only Please refer to Chapter 2 7 for detailed register description System Bank The register address range associated with the system bank parameters is 0x28 0x2E The...

Page 16: ...according to the parameters exported from RFPDK Users need follow the procedure of read modify write to set an individual bit to 1 or 0 2 The blue area indicates that users need to understand it The r...

Page 17: ...g from 0 256 bits 2 Notes 1 Preamble adopts NRZ format without encoding e g for 0x55 the data flow is 0b01010101 at the set rate 0 represents low level and 1 represents high level 2 Head Sync stop bit...

Page 18: ...lue in 0 255 0 represents that sending 1 byte of Preamble and so on 255 represents that it sends preamble with 256 bytes For users if the PREAMBLE_EN is 0 a preamble is not sent and if the configurati...

Page 19: ...is not sent and if the sync enabling bit is 1 a sync of 1 32 symbols is sent 2 7 5 Addr ID Table 11 Addr ID Related Registers Register Name Bits R W Bit Name Function Description CUS_PKT13 0x14 4 0 RW...

Page 20: ...he table tick indicates a register to be filled For example If ADDR_LENGTH is set to 15 the length is 16 logic bits and the value is 0x5678 Then users will fill the value into ADDR_ID 31 24 and ADDR_I...

Page 21: ...IT_LOGIC_L 7 4 is 0b 1000 and BIT_LOGIC_H 7 4 is 0b 1110 Expand ADDR_ID as symbol then the Tx data is as follows 1000_1110_1000_1110_1000_1110_1110_1000_1000_1110_1110_1110_1110_1000_1000_1000_1110_10...

Page 22: ..._LENGTH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 1 2 3 4 5 6 7 For users if the KEY_EN is 0 the key value is not sent If the configuration is 1 the key value of 1 8 logic bits is sent 2 7 7 LBD Statu...

Page 23: ..._RESULT got by the test if LBD_RESULT is smaller than LBD_TH it indicates the low voltage occurs on the contrary it is the normal voltage According to the comparison result the LBD indicating signal w...

Page 24: ...to switch to STBY status first and then switch to Tx status to trigger the measurement process 2 LBD_RESULT can be used as a condition for judgment Therefore users can use LBD_RESULT as a quantitativ...

Page 25: ...S_PKT29 0x24 7 0 RW INTERVAL_LENGTH 7 0 The Interval length can be configured to 0 255 0 represents sending 0 of 1 symbol and so on 255 represents sending 0 of 256 symbols The Symbol length is random...

Page 26: ...in the above figure That is a preamble appears once in a group locating at the beginning of each group and preamble appears M times M TXCYCLE within one transmission cycle If Both Tcycle and preamble...

Page 27: ...e which involves chip state switching state reading reset etc 2 8 1 Soft Reset 0xFF is written to CUS_SOFTRST 0x2F through the SPI bus which can fulfill the RF part reset processing Table 23 Soft Rese...

Page 28: ...rations The oscillator keeps running Notes 1 CFG refers to the process for configuring chip operating parameters through SPI for the MCU 2 CALS refers to the process for calibrating the analog module...

Page 29: ...0 RFDIN as high resistance input Configure PC1 SDIO as output 0 4 After initialization the chip can enter low power based sleep state or perform other processing 2 9 2 Tx Process The CMT2189B hardware...

Page 30: ...fy individual registers for example write 0x88 to ADDR_ID 7 0 as the key value 4 Set register 0x34 5 to 0 then set register 0x2A 1 0 to 0 b00 5 Send the go_tx command through SPI and start the chip to...

Page 31: ...6 Set the register 0x34 5 to 0 and then set the register 0x2A 1 0 to 0b01 7 Send the command go_tx through SPI and start the chip transmission according to above configurations it is recommended to wa...

Page 32: ...3 RW DATAIN_EN Data Input Enabling bit for RFDIN Tx mode 0 disable 1 enable In the pass though mode the data transmitting rate is controlled by RFDIN PC0 When PC0 keeps output 0 for more than the tim...

Page 33: ...FCFGx therefore the total space is 64 k Words which are all EEPROM Among them 0 0x7FF is the main program bank and 0x800 0x1FFF is the reserved bank which is not implemented User and factory configur...

Page 34: ...0 0000 0000 3 STATUS PAGE TF PF Z HC C 01 1xxx 4 FSR Indirect data memory address pointer 5 PORTA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 00x0 0000 6 7 PORTC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0000 0000 8 9 A P...

Page 35: ...data memory using the content of SFR non physical registers xxxx xxxx 81 OPTION PAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 82 PCL Program Counter 7 0 0000 0000 83 STATUS PAGE TF PF Z HC C 0 1 1...

Page 36: ...M access Bank0 s 0x70 0x7F xxxx xxxx Notes 1 INDF is not a physical register 2 The gray part is not implemented yet please do not access 3 indicates that it is not implemented yet Please do not use or...

Page 37: ...truction execution 2 Z Zero flag bit 1 the result of arithmetic operation or logic operation is 0 0 the result of arithmetic operation or logic operation is not 0 1 HC Half carrying borrowing ADDWF AD...

Page 38: ...nstruction using a state register as the target register the status content may be different than intended 2 It is suggested to change the status register using the BCR BSR SWAPR and STR instructions...

Page 39: ...a 1 PC1 PORTC1 data 0 PC0 PORTC0 data Bit Name Function 7 GIE Global interrupt enabling bit 1 enable all enabled interrupts 0 disable all interrupts 6 PEIE Peripheral interrupt enabling bit 1 enable a...

Page 40: ...ite operation does not complete 6 CKMEAIF Interrupt flag bit for the operation of fast clock measuring slow clock 1 the operation of fast clock measuring slow clock completes must be cleared in softwa...

Page 41: ...0000 1 1 post dividing ratio 0001 1 2 post dividing ratio 0010 1 3 post dividing ratio 0011 1 4 post dividing ratio 0100 1 5 post dividing ratio 0101 1 6 post dividing ratio 0110 1 7 post dividing ra...

Page 42: ...Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CMCON0 C2OUT C1OUT C2INV C1INV CIS CM 2 0 Reset 0 0 0 0 1 0 0 0 Type R R RW RW RW RW RW RW Bit Name Function 7 5 Reserved bits read as 0 4 1 WDTPS 3 0 Watchdog time...

Page 43: ...output control bit 0 no reverse 1 reverse 3 CIS Comparator input switching bit When CM 2 0 010 1 C1IN connects to C1VIN C2IN connects to C2VIN 0 C1IN connects to C1VIN C2IN connects to C2VIN When CM...

Page 44: ...d in compiling option SLVREN 1 means LVR is enabled in operating mode and automatically disabled in sleep mode SLVREN 0 means LVR is always enabled 2 When LVREN is disabled in compiling option LVR is...

Page 45: ...set 1 1 1 1 1 111 Type RW RW RW RW RW RW Table 56 OPTION Bit Function Description Bit Name Function 11 0 SOSCPR 11 0 oscillator period unit number of fast clock period is used for slow clock measureme...

Page 46: ...e selection 1 trigger count on the falling edge of PA2 T0CKI 0 trigger count on the rising edge of PA2 T0CKI 3 PSA Prescaler assignment bit 1 prescaler is assigned to WDT 0 prescaler is assigned to Ti...

Page 47: ...peration completion interrupt enabling bit 1 enable write operation completion interrupt 0 disable write operation completion interrupt 6 CKMEAIE Fast clock measuring slow clock operation completion i...

Page 48: ...it0 OSCCON LFMOD IRCF 2 0 OSTS HTS LTS SCS Reset 0 101 1 0 0 0 Type RW RW R R R RW 1 TMR2IE Timer 2 and PR2 compare matching interrupt enabling bit 1 enable 0 disable Bit Name Function 1 POR Power on...

Page 49: ...default 100 2 MHz 011 1 MHz 010 500 kHz 001 250 kHz 000 32 kHz LFINTOSC 3 OSTS Oscillator start up timeout status bit 1 device is running from the external system clock defined by the FOSC 2 0 0 devi...

Page 50: ...t3 Bit2 Bit1 Bit0 IOCA IOCA 7 0 Reset 0x00 Type RW Table 72 IOCA Bit Function Description 4 1 25 VRCON Addr 0x99 Table 73 VRCON Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 VRCON VREN VRR VR...

Page 51: ...Bit0 EEADR EEADR 7 0 Reset 0x00 Type RW 4 1 28 EECON1 Addr 0x9C Table 77 EECON1 Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EECON1 WREN3 WREN2 WRERR WREN1 RD Reset 0 0 X 0 0 Type RW RW RW RW...

Page 52: ...enable programming EEPROM by software Each bit will restore to 0 automatically after programming completes Other values disable programming EEPROM by the software 3 WRERR Data EEPROM write operation...

Page 53: ...3 WDTE 1 enable WDT the program cannot disable it 0 disable WDT but the program can enable WDT by setting the SWDTEN bit of the WDTCON 2 0 FOSC 2 0 000 32 k crystal oscillator mode The PA6 PA7 connect...

Page 54: ...re shown in the below figure It should be notified that for the LCALL and LJUMP instructions on the right side of the figure PCLATH is not required since the operating code in the instructions is 11 b...

Page 55: ...gram branch table namely calculate the LJUMP Assuming that the PCLATH is set as the start address of the table and the table length is greater than 255 instructions or if the lower 8 bits of the memor...

Page 56: ...or LFINTOSC These clocks or oscillators combined with prescalers can provide the system with a variety of frequency clock sources The prescaler ratio of the system clock source can be controlled by th...

Page 57: ...cts the high gain settings of the internal inverter amplifier 5 3 Internal Clock Mode The oscillator mode has 2 independent internal oscillators which can be configured or selected as the system clock...

Page 58: ...art up delay 3 The clock switching circuit waits for the arrival of the falling edge of the current clock 4 Keep CLKOUT to low the clock switching circuit waits for the arrival of 2 falling edges of t...

Page 59: ...P or XT mode 5 5 Two Speed Clock Start up Mode The two speed start up mode reduces the power consumption further by minimizing the latency between the external oscillator and the code execution For ap...

Page 60: ...tor 5 OSTS is set to 1 6 The system clock keeps low until the next falling edge the new clock arrives LP or XT mode 7 The system clock is switched to the external clock source 5 6 Fail Safe Clock Moni...

Page 61: ...instruction or a reverse of the SCS bit of the OSCCON register After the SCS bit of the OSCCON register is modified the OST will be restarted When OST runs the device continues to operate with the IN...

Page 62: ...eep MCLR reset during normal operating Brown out reset BOR WDT watchdog sleep wakeup will not result in the same reset due to the WDT watchdog timeout during normal operating Since WDT sleep wakeup it...

Page 63: ...operate properly PWRT can also be enabled by the system CONFIG register UCFG0 When the low voltage reset function is enabled users should also enable PWRT The PWRT timing is triggered by a VDD voltag...

Page 64: ...s low for a long enough time Pulling the MCLR high will make the CPU to start the executing immediately which is useful for testing or implementing multiple MCU synchronization PCON Power Control Regi...

Page 65: ...After POR or BOR if PWRTEB UCFG0 4 is low PWRT is active which keeps 2048 internal slow clock cycles about 64 ms 2 The TBOR time is about 157 us 3 After the voltage is restored to normal the internal...

Page 66: ...tek com Table 88 STATUS PCON Bit Description U no change X unknown POR BOR TO PD Condition 0 X 1 1 POR U 0 1 1 BOR U U 0 U WDT Reset U U 0 0 WDT Wake up U U U U MCLR reset during normal operation U U...

Page 67: ...T After POR or BOR it inserts a state and maps the program EEPROM units starting from 2000H into configuration registers The system reset is released until the end of the BOOT as shown in Figure 19 an...

Page 68: ...ower on process or it can be written through the external serial port The CLRWDT instruction for clearing the watchdog and SLEEP instruction will clear the watchdog counter In the case of enabling the...

Page 69: ...r is assigned to Timer 0 Notes 1 When the value of PSA is changed the hardware will clear the prescaler automatically WDT Set flag bit T0IF On overflow PSA WDTPS 3 0 16 bit Prescaler 8bit WDT Time out...

Page 70: ...ere are 8 prescale ratios 1 2 to 1 256 which can be set by the PS 2 0 bit of the OPTION register Notes 1 The prescaler circuit is neither readable nor writable Any write operation on the TMR0 register...

Page 71: ...leep 9 3 3 Timer 0 Driven by External Clock In the counter mode the synchronization between the T0CKI pin input and the Timer 0 register is fulfilled by sampling the phase of the internal clock Q1 and...

Page 72: ...d PR2 are compared constantly to determine when to match The TMR2 will increase from 00h until it matches the PR2 The followings will occur when they match TMR2 is reset to 0x00 in the next cycle for...

Page 73: ...www cmostek com 5 The prescaler counter and postscaler counter will be cleared when the following registers are written Write the TMR2 Write the T2CON Any reset action 6 Writing the T2CON does not cle...

Page 74: ...shown in the below figure since the functional pins are used in the RF serial control bus Comparator reset after POR CM 2 0 0b000 Off Off C1IN C1IN C2IN C2IN A A A A Comparator switched off with the...

Page 75: ...formed before the data EEPROM is used either read or write that is write double 0xAA to an unused EEPROM unit and make sure the program will no longer operate this unit after then The code example is...

Page 76: ...tem clock2 Fosc The operation steps are as follows 1 To improve the measurement accuracy it is suggested that IRCF is set to 111 and SCS is set to 1 and the system clock of 16 M is selected 2 Set T2CO...

Page 77: ...om Q Q SET CLR S R Q Q SET CLR S R Q Q SET CLR S R 0 1 BUS 1 MSCKCON WR CKMAVG 0 1 Q Q SET CLR S R T2 SYSCLK CKMEAS EN TMR2 16 bit SOSCPR 11 0 SYSCLK T1 MEAS DONE To INT CKCNTI Figure 26 Block Diagram...

Page 78: ...ollowing interrupt flag bits INT pin interrupt PORTA change interrupt Timer 0 overflow interrupt PIR1 contains the peripheral interrupt flag bit and PIE1 contains its corresponding interrupt enabling...

Page 79: ...input The pin configured as an analog input is always read as 0 2 When initializing the level change interrupt configure it as a digital input IO first and set the corresponding IOCA to 1 then read t...

Page 80: ...2 IOC RA3 IOCA3 IOC RA4 IOCA4 IOC RA5 IOCA5 IOC RA6 IOCA6 IOC RA7 IOCA7 TMR2IF TMR2IE EEIF EEIE CKMEAIF CKMEIE C1IF C1IE C2IF C2IE OSFIF OSFIE PEIE T0IF T0IE INTF INTE RAIF RAIE GIE Wakeup If in sleep...

Page 81: ...function when the crystal mode or external clock mode is configured namely clear the FCMEN bit of the UCFG1 Meanwhile the configuration bit CM 2 0 of the comparator is written as 0b111 to switch off t...

Page 82: ...ak pull up option are available for each port of PORTA 16 2 1 Weak Pull Up Each port of PORTA except for PORTA 5 has an internal weak pull up function that can be set individually Controlling the bit...

Page 83: ...IO serial port clock for debug PA0 Serial port data for Debug PA1 External interrupt input PA2 External clock source for Timer0 PA2 The following figure describes The internal circuit architecture of...

Page 84: ...the port is shown in the below figure RD TRISA WR WPUA Data Bus VDD RD WPUA WR PORTA RAPU VDD WR TRISA RD PORTA WR IOCA RD IOCA Interrupt On Change D Q Q _ D Q Q _ RD PORTA Qn ATEST1 EN ATEST1 EN D C...

Page 85: ...the below figure D CLK Q Q _ RD TRISA WR WPUA Data Bus VDD D CLK Q Q _ D CLK Q Q _ RD WPUA WR PORTA RAPU VDD WR TRISA RD PORTA D CLK Q Q _ WR IOCA RD IOCA Interrupt On Change D Q Q _ D Q Q _ RD PORTA...

Page 86: ...3 5 PORTA7 PA7 PA7 can be configured as the following functional port GPIO Crystal oscillator and resonator connection Clock input The internal circuit architecture of the port is shown in the below...

Page 87: ...ta of RF part SPI for PC4 only Comparator input for PC0 and PC1 only however it is not available since the ports are used to control the RF part Comparator output for PC4 only however it is not availa...

Page 88: ...R 4 7 d NONE I N C R R d 1 Increment reg R 1 d Z I N C R S Z R d 1 2 Increment reg skip if 0 R 1 d NONE A D DW R R d 1 Add W and reg W R d C HC Z S U BW R R d 1 Sub W from reg R W d R W 1 d C HC Z DEC...

Page 89: ...on Status R E T W I 2 Return place imm to W Stack PC I W NONE A D D W I I 1 Add imm to W W I W C HC Z SUBW I I 1 Subtract W from imm I W W C HC Z Notes 1 The TMODE register of the chip refers to the O...

Page 90: ...ial release 2017 11 23 1 1 2 Increase the Section 2 7 1 Tx rate description 2017 11 29 1 2 All PC4 RFDIN is modified as PC0 RFDIN 2018 01 09 1 3 4 1 14 4 1 30 Update the function description of SLVREN...

Page 91: ...d for inaccuracies and specifications within this document are subject to change without notice The material contained herein is the exclusive property of CMOSTEK and shall not be distributed reproduc...

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