AN201
Rev 1.5 | 64/91
www.cmostek.com
6.5 Error Instruction Reset
When the instruction register of the CPU obtains an undefined instruction, the system will have reset, which help improve the
system anti-interference ability.
6.6 Timeout Action
During the power-on process, the internal timeout action sequence of the chip is as follows. The PWRT timing is started after the
POR ends. As the timing is started by the POR pulse, a timeout will occur if the /MCLR keeps low for a long enough time. Pulling
the /MCLR high will make the CPU to start the executing immediately, which is useful for testing or implementing multiple MCU
synchronization.
PCON
（
Power Control Register
）
There are 2 state bits in the PCON register to indicate what type of reset occurs. Bit 0 is the /BOR bit, of which the state is
unknown upon power-on reset, thus the software must set it to 1 and check whether it is 0 then. Bit 1 is the /POR indication bit,
which is 0 upon power-on reset, and the software must set it to 1.
Figure 19. Power-on Reset with MCLRB
1
2
3
4
5
6
7
8
9
10
VDD
POR_RSTN
4ms delay
BOOT_EN
PWRTE
BOOT_END
PWRT_OV
MCLRB
SYS_RSTN
PWRT,64ms
