AN201
Rev 1.5 | 25/91
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Table 19. Relationship between Stop Bit Length Selection and Bit Enabling
STOP_BIT
STOP_LENGTH
<15:8>
<7:0>
0~7
√
8~15
√
√
In the table, tick indicates a register to be filled. For example, if STOP_LENGTH is set to 7, that is, the length is 8 symbols, and
the value is 0x56. Then users will fill this value into STOP_BIT[15:8]. MSB corresponds to the 15
th
bit, and LSB corresponds to
the 18
th
bit.
For users, if STOP_EN is configured to 0, stop bits are not sent. If it is configured to 1, stop bits with 1-8 symbols are sent.
2.7.9 Pause/Interval Configuration
Table 20. Pause/Interval Configuration Register
Register Name
Bits
R/W
Bit Name
Function Description
CUS_PKT1
(0x08)
6
RW
INTERVAL_EN
Interval enabling bit.
0: disable
1: enable
CUS_PKT29
(0x24)
7:0
RW
INTERVAL_LENGTH<7:0>
The Interval length can be configured to 0 ~ 255.
0 represents sending 0 of 1 symbol, and so on,
255 represents sending 0 of 256 symbols.The
Symbol length is random.
Note that interval is fixed to sending 0.
Notes
1.
In a strict sense, pause/interval is not an effective part of the packet structure, namely, it only sends a number of symbols of
0.
2.
For users, if INTERVAL_EN is configured to 0, pause/interval is not sent. If it is configured to 1, a pause/interval with 1 ~
256 symbols is sent.
2.7.10 Tcycle Configuration
Tcycle refers to a transmission cycle (transmission process) in hardware packet Tx mode. A transmission cycle can contain
several (N) repeated packet transmissions with the support of pause/interval between packets. It also supports transmitting m
data groups in a transmission cycle with each data group composed of N packets. The different transmission cycle configurations
are shown in the below figure.
