AN201
Rev 1.5 | 58/91
www.cmostek.com
32 kHz
5.3.2 Clock Switching Timing of HFINTOSC and LFINTOSC
When switching between LFINTOSC and HFINTOSC, the new oscillator may be in shut-down state to save power as shown in
Figure 144, Figure 155. In this case, there is a delay between the IRCF bit of the OSCCON register being modified and the
frequency selection taking effect. The LTS and HTS bits of the OSCCON register indicate the current state of the LFINTOSC and
HFINTOSC oscillators. The frequency selection timing is as follows.
1.
The IRCF<2:0> bit of the OSCCON register is modified.
2.
If the new clock is shut down, start a clock start-up delay.
3.
The clock switching circuit waits for the arrival of the falling edge of the current clock.
4.
Keep CLKOUT to low, the clock switching circuit waits for the arrival of 2 falling edges of the new clock.
5.
The CLKOUT is connected with the new clock now, and the HTS and LTS bits of the OSCCON register are updated as
required.
6.
The clock switch completes.
HFINTOSC
LFINTOSC
IRCF = 0
IRCF
≠
0
HFINTOSC
startup time
Switch after 2
cycles
IRCF
SYSCLK
Figure 14. Switch from Slow Clock to Fast Clock
LFINTOSC
HFINTOSC
IRCF = 0
IRCF
≠
0
IRCF
SYSCLK
LFINTOSC
Startup time
Switch after 2
cycles
Figure 15. Switch from Fast Clock to Slow Clock
5.4 Clock Switching
Users can switch the system clock source between the external and internal clock sources by operating the system clock
selection (SCS) bit of the OSCCON register via software.
