SCA Logic
The FPGA uses the signals from the LLD and ULD comparators to determine if an in-
put pulse satisfies any of the windows set for the three SCAs. The logic can most eas-
ily be described by the timing diagram in Figure 20. If an input causes an LLD
crossing without a subsequent ULD detection before the peak is signaled, an SCA
pulse can be generated.
An important point to note is that as count rates increase, it is likely that some pulses
may not cause an LLD crossing because the previous pulse has not fallen below the
LLD threshold; for this reason, the pulse shaping must be set consistent with the input
count rate. As noted earlier, the peak signal is derived from the bipolar shaping ampli-
fier and give a timing reference after the peak of the unipolar signal.
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Triple Channel Analyzer
Figure 20 SCA Timing Diagram
