Inhibit Input
This input is usually generated during the recovery time associated with TRP or opti-
cal reset preamplifiers. During its active pulse width, the automatic threshold deter-
mining circuits, the baseline restorer and all SCAs are gated off.
Triple Channel Analyzer
Computer Controlled Logic
Computer control of the Triple Channel Analyzer (TCA) is provided by the Field Pro-
grammable Gate Array (FPGA) U6 and three dual DACs U7, U8 and U9. U6 provides
the interface to the ICB and contains the registers required to hold the configuration of
the SCA.
U3 is a nonvolatile RAM which contains the module Type ID and module serial num-
ber.
SW1 is a 16-position binary-encoded rotary switch which sets the module’s ICB ad-
dress.
U7 through U9 are dual 12-bit serial DACs whose output are the LLD and ULD levels
that determine each SCA energy window. These DACs are loaded by the FPGA with
values it receives from the ICB. Each dual-DAC is loaded by sending it 24 clock
pulses (SCLK) that shift in a data code on DIN; the accompanying chip select (CSn*)
determines which of the three dual-DACs is loaded.
The DAC reference voltage (–3.5 volts) is obtained using a precision reference in a
Zener diode configuration. Jumpers JP5, JP6 and RV1 select and adjust the DAC ref-
erence voltage.
SCA Front End
Input pulse discrimination is accomplished using six high speed comparators U10
through U15. Three precision voltage dividers in parallel split and scale the unipolar
input pulse to be compatible with the DAC reference level. Comparators U10, U12,
and U14 (schematic sheet 2) discriminate between the scaled unipolar signal and upper
reference level (ULD) producing a TTL positive logic level when the unipolar signal is
above the ULD level. U11, U13 and U15 (schematic sheet 2) discriminate between the
scaled unipolar signal and lower reference level (LLD) producing a TTL positive logic
level when the unipolar signal is above the LLD level.
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Circuit Description
