Caen N6724, User Manual

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PLL Mode
The Phase Detector within the AD9520 device allows to couple REF-CLK with an internal VCXO, which pro-
vides the nominal ADCs frequency (100 MHz).
As introduced in Sec. Clock Distribu on , the source of the REF-CLK signal (see Fig. 7.2 ) can be external on
CLK-IN front panel connector or internal from the 50 MHz local oscillator.
The following op ons are allowed:
1. 50 MHz internal clock source - this is the standard opera on mode: the AD9520 dividers do not
require to be reprogrammed (the digi zer works in the AD9520 default configura on). The clock
source selec on bit (bit[6] of 0x8100
[RD1] ) is in default INT mode. REF-CLK = OSC-CLK.
2. 50 MHz external clock source - in this case, the clock source is taken from an external device; the
AD9520 dividers do not need to be reprogrammed as the external frequency is the same as the default
one. The clock source selec on bit (bit[6] of 0x8100
[RD1] ) must be set in EXT mode. CLK-IN = REF-CLK
= OSC-CLK.
3. External clock source different from 50 MHz - the clock source is externally provided as in point 2, but
the AD9520 dividers must now be reprogrammed to lock the the VCXO to the new REF-CLK in order
to provide out the nominal sampling frequency at 100 MHz. The clock source selec on bit (bit[6] of
0x8100
[RD1] ) must be set in EXT mode. CLK-IN = REF-CLK
̸
= OSC-CLK.
If the digi zer is locked, the PLL-LOCK front panel LED must be on.
Note : the user who wants to work as in point 3, please contact CAEN (see Chap. Technical Support ) indicat-
ing the required reference clock frequency, to check its feasibility and then receive the PLL programming
file. The “Upgrade PLL” func on in CAENUpgrader so ware tool can be used to update the digi zer PLL
[RD4] .
Reducing the Sampling Frequency
In case the board is required to work at a sampling frequency (SAMP-CLK) lower than the nominal, it can
be achieved in one of the fallowing ways:
1. direct: reprogramming the AD9520 dividers. REF-CLK can be configured as in Sec. PLL Mode . Not
all the frequencies are admi ed and a lower frequency limit must be considered, due to the internal
electronics. Please contact CAEN (see Sec.
Technical Support ) to check the feasibility.
2. indirect: enabling the Decima on op on in the firmware (see Sec. Decima on ).
22 UM3247 - N6724 User Manual rev. 10