Caen N6724 User Manual Download Page 56

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10 HW Installa on

• The Module ﬁts into all NIM crates

•

Use only crates with forced cooling air ﬂow

• Turn the crate OFF before board inser on/removal

• Remove all cables connected to the front panel before board inser on/removal

CAUTION

: this product needs proper cooling.

USE ONLY CRATES WITH FORCED COOLING AIR FLOW SINCE
OVERHEATING THE BOARD MAY DEGRADE ITS PERFORMANCES!

CAUTION

: this product needs proper handling.

N6724 DOES NOT SUPPORT LIVE INSERTION (HOT SWAP)!
REMOVE OR INSERT THE BOARD WHEN THE NIM CRATE IS POWERED
OFF!

ALL CABLES MUST BE REMOVED FROM THE FRONT PANEL BEFORE
EXTRACTING THE BOARD FROM THE CRATE!

UM3247 - N6724 User Manual rev. 10

Summary of Contents for N6724

Page 1: ...User Manual UM3247 N6724 2 4 Channel 14bit 100 MS s Waveform Digitizer Rev 10 January 27th 2017...

Page 2: ...and Sec TRG IN as Gate Symbols Abbreviated Terms and Notation ADC Analog to Digital Converter AMC ADC Memory Controller DAQ Data Acquisi on DAC Digital to Analog Converter DC Direct Current LVDS Low...

Page 3: ...ies CAEN SpA reserves the right to modify its products speci ca ons without giving any no ce for up to date informa on please visit www caen it MADE IN ITALY We stress the fact that all the boards are...

Page 4: ...2 Decima on 23 Trigger Clock 23 Acquisi on Modes 24 Acquisi on Run Stop 24 Acquisi on Triggering Samples and Events 24 Mul Event Memory Organiza on 26 Custom size events 26 Event structure 27 Header 2...

Page 5: ...n Status 57 11 Firmware and Upgrades 58 Firmware Upgrade 58 Firmware File Descrip on 59 Troubleshoo ng 59 12 Technical Support 60 Returns and Repairs 60 Technical Support Service 60 List of Figures Fi...

Page 6: ...Majority level 1 and TTVAW 0 42 Fig 7 18 Trigger con gura on of TRG OUT front panel connector 43 Fig 8 1 Drivers and so ware layers 49 Fig 9 1 CAENUpgrader Graphical User Interface 50 Fig 9 2 CAENComm...

Page 7: ...G THE BOARD MAY DEGRADE ITS PERFORMANCES CAUTION this product needs proper handling N6724 DOES NOT SUPPORT LIVE INSERTION HOT SWAP REMOVE OR INSERT THE BOARD WHEN THE NIM CRATE IS POWERED OFF ALL CABL...

Page 8: ...self trigger when the input signal goes under over a programmable threshold The trigger from one board can be propagated out of the board through the front panel GPO During the acquisi on data stream...

Page 10: ...nnels ROC FPGA Readout control Optical link control USB interface control Trigger control External interface control MUX OSC CLOCK MANAGER AD9520 LOCAL BUS CLK IN TRG IN GPI USB INPUTS FRONT PANEL GPO...

Page 11: ...II AC coupled di eren al input clock LVDS ECL PECL LVPECL CML single ended NIM TTL to di eren al adapter available by A318 accessory Ji er 100 ppm requested GPO LEMO General purpose digital output NIM...

Page 12: ...c vely A2818 or A3818 USB USB 2 0 compliant Up to 30 MB s transfer rate SUPPORTED FIRMWARE DPP PHA for the Pulse Height Analysis DPP DAW for the Dynamic Acquisi on Window FIRMWARE UPGRADE Firmware can...

Page 13: ...4 Packaging and Compliancy The module is housed in a single width NIM unit Fig 4 1 Front view Fig 4 2 Side view UM3247 N6724 User Manual rev 10 13...

Page 14: ...CAUTION this product needs proper handling N6724 DOES NOT SUPPORT LIVE INSERTION HOT SWAP REMOVE OR INSERT THE BOARD WHEN THE NIM CRATE IS POWERED OFF ALL CABLES MUST BE REMOVED FROM THE FRONT PANEL B...

Page 15: ...quirements The table below resumes the N6724 power consump ons per relevant power supply rail MODULE SUPPLY VOLTAGE 6 V 6 V N6724 3 9 A 90 mA Tab 5 1 Power requirements table UM3247 N6724 User Manual...

Page 16: ...6 Panels Descrip on Fig 6 1 Front panel view 16 UM3247 N6724 User Manual rev 10...

Page 17: ...Sign type di eren al LVDS ECL PECL LVPECL CML CAEN provides single ended to di eren al A318 cable adapter see Tab 1 1 Coupling AC CLK IN Zdiff 100 PINOUT CLK IN LED GREEN indicates the external clock...

Page 18: ...PL 00 250 NTN Manufacturer LEMO OPTICAL LINK PORT FUNCTION Op cal LINK connector for data readout and ow control Daisy chainable Compliant with Mul mode 62 5 125 m cable featuring LC connectors on bot...

Page 19: ...Run Stop TRG GREEN indicates the trigger is accepted DRDY GREEN indicates the event data is present in the Output Bu er BUSY RED indicates all the bu ers are full for at least one channel LABELS A bl...

Page 20: ...and 5 0 V at 10 Vpp The input bandwidth ranges from DC to 40 MHz with 2nd order linear phase an aliasing low pass lter MCX OpAmp 50 DAC Vref 14 bit ADC Input FPGA 1 125 0 2 25 1 125 2 25 Input Dynamic...

Page 21: ...e selec on can be done by wri ng bit 6 of register 0x8100 RD1 between the following modes INT mode default means REF CLK is the 50 MHz of the local oscillator REF CLK OSC CLK EXT mode means REF CLK so...

Page 22: ...provided as in point 2 but the AD9520 dividers must now be reprogrammed to lock the the VCXO to the new REF CLK in order to provide out the nominal sampling frequency at 100 MHz The clock source selec...

Page 23: ...med threshold see Sec Self Trigger So ware trigger and external trigger are not a ected by decima on op on While the real sampling frequency does not change i e 100 MS s the decima on e ect is to chan...

Page 24: ...ncrement the EVENT COUNTER ll the ac ve bu er with the pre post trigger samples whose number is programmable via register address 0x8114 the acquisi on window width also referred to as record length i...

Page 25: ...n and the acquisi on con nues wri ng on it The EVENT COUNTER can be programmed in order to be either incremented or not If this func on is enabled the EVENT COUNTER value iden es the trigger number se...

Page 26: ...ne bu er where k 1024 and M 1024 1024 Having 512 kS memory size as reference this means that each bu er contains 512k Nb samples e g Nb 1024 means 512 samples in each bu er Custom size events In case...

Page 27: ...s 22 21 at register address 0x811C see Tab 7 2 REGISTER 0x811C Bits 22 21 FUNCTIONAL DESCRIPTION Reserved TRG OPTIONS INFORMATION 16 bits in the 2nd header word 00 default Reserved Must be 0 01 Event...

Page 28: ...The trigger me tag is reset either at the start of acquisi on or via front panel signal on S IN or LVDS I O connectors and increments with 100 MHz frequency i e at each ADC clock cycle The TTT value i...

Page 29: ...ERVED TRG OPTIONS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EVENT SIZE TRIGGER TIME TAG 1 0 1 0 EVENT COUNTER HEADER 1 SIZE CONTROL WORD CONTROL WORD D AT A...

Page 30: ...tely accept a new trigger This way the FULL re ects the BUSY condi on of the board i e inability to accept triggers Note when bit 5 1 the minimum number of circular bu ers to be programmed is Nb 2 In...

Page 31: ...n the readout All events are acquired with the common trigger and saved into the board memory During the readout the FPGA analyses the event and transfers it when the zero suppression condi on is veri...

Page 32: ...is not available among the read out data As in the example reported in Fig 7 5 in case of 4 channels if the integral of channel 0 and channel 2 are over ZS_Threshold TINT the corresponding samples ar...

Page 33: ...of 4 channels Channel 0 and channel 2 are over ZS_Threshold TAMP for at least Ns samples NOVT and the corresponding channels are wri en in the output data Sam ples from channel 1 are not over threshol...

Page 34: ...including the size itself The control word has the following format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RESERVED NUMBER OF SKIPPED SAMPLES SKIP CONT...

Page 35: ...28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIZE CH0 NSKIP1 0 RESERVED NGOOD1 1 RESERVED SAMPLESGOOD1 NSKIP2 0 RESERVED NGOOD2 1 RESERVED SAMPLESGOOD2 NSKIP3 0 RESERV...

Page 36: ...D2 NLBK N3 NLFWD 1 RESERVED SAMPLESGOOD2 DATA CHx HEADER N2 0 RESERVED N4 0 RESERVED NGOOD3 NLBK N5 1 RESERVED SAMPLESGOOD3 Fig 7 10 Event format for non overlapping NLBK and NLFWD in case of posi ve...

Page 37: ...nd N3 NLFWD N5 Note In this case there are two subsequent GOOD intervals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIZE CHx N1 NLBK 0 RESERVED NGOOD1 NLBK N...

Page 38: ...ory Buffers ADC Digital Thresholds 4 Local Bus Interface Mother Board x2 mezzanines x2 channels Fig 7 13 Block diagram of Trigger management So ware Trigger External Trigger Self trigger Coincidences...

Page 39: ...trigger is therefore delayed by Nth quartets of samples with respect to the input signal see Fig 7 14 The individual self triggers from all channels are propagated to the central trigger logic on the...

Page 40: ...smaller than the number of channels enabled via bits 3 0 mask By default bits 26 24 00 i e Majority level 0 which means the coincidence acquisi on mode is disabled and the TTVAW is meaningless In thi...

Page 41: ...ela onship with Majority level 1 and TTVAW 0 Fig 7 17 shows the trigger management in case the coincidences are enabled with Majority level 1 and TTVAW 0 i e 1 clock cycle Note CAEN provides a guide t...

Page 42: ...OLD SELF TRG CH0 SELF TRG CH1 CH0 enabled IN CH0 THRESHOLD TRIGGER Maj lev 1 CH1 enabled IN OR signal TTVAW Fig 7 17 Self trigger rela onship with Majority level 1 and TTVAW 0 42 UM3247 N6724 User Man...

Page 43: ...nal Trigger par cipate in the common acquisi on trigger refer to the red path on top of Fig 7 18 SELF TRG 3 0 GPO 0x8110 Bits 9 8 00 01 10 TO THE CHANNELS COMMON ACQUISITON TRIGGER 0x811C Bits 17 16 4...

Page 44: ...nable the desired self trigger as Trigger Out signal on board n by bits 3 0 mask Disable So ware Trigger External Trigger as Trigger Out signal on board n bits 31 30 00 Set Trigger Out signal as the O...

Page 45: ...e Output Bu er the event counter and performs a FPGAs global reset which restores the FPGAs to the default con gura on It ini alizes all counters to their ini al state and clears all detected error co...

Page 46: ...nica on link not supported by USB Using Polling interrupts disabled by performing periodic read accesses to a speci c register of the board it is possible to know the number of events present in the b...

Page 47: ...h etc wrong parameter se ngs cause Bus Error Bit 3 at register address 0xEF00 RD1 enables the module to broadcast an interrupt request on the Op cal Link the enabled Op cal Link Controllers propagate...

Page 48: ...ge all the relevant board se ngs DPP parameters con gura on data acquisi on storage Con gura on of synchronized start stop acquisi on is supported in mul board hardware setup as well as the single boa...

Page 49: ...ollowing communica on channels Fig 8 1 PC USB N6724 PC PCI A2818 CONET N6724 PC PCIe A3818 CONET N6724 WHEN TO INSTALL CAEN LIBRARIES WINDOWS compliant CAEN so ware NOT CAEN so ware for Windows OS are...

Page 50: ...on the CAENComm and CAENVMELib libraries see Chap Drivers Libraries and re quires third party Java SE 8 update 40 or later to be installed Fig 9 1 CAENUpgrader Graphical User Interface CAENUpgrader in...

Page 51: ...e Demo is included in the CAENComm library installa on Windows package which can be downloaded on CAEN web site login required at Home Products Firmware So ware Digi zer So ware So ware Libraries CAEN...

Page 52: ...trongly recommended to all those users willing to write the so ware on their own Fig 9 3 CAEN WaveDump The installa on packages can be downloaded on CAEN web site login required at Home Products Firmw...

Page 53: ...nd restore the program se ngs Fig 9 4 CAENScope main frame CAENScope installa on packages can be downloaded on CAEN web site login required at Home Products Firmware So ware Digi zer So ware Readout S...

Page 54: ...oring of the acquisi on and histograms Moreover it is able to perform advanced mathema cal analysis on both the ongoing histograms and col lected spectra peak search background subtrac on peak ng ener...

Page 55: ...re apply energy and PSD cuts calculate and show the sta s cs trigger rates data throughput etc save the output data les raw data lists waveforms spectra and use the saved les to run o line with di ere...

Page 56: ...CAUTION this product needs proper cooling USE ONLY CRATES WITH FORCED COOLING AIR FLOW SINCE OVERHEATING THE BOARD MAY DEGRADE ITS PERFORMANCES CAUTION this product needs proper handling N6724 DOES NO...

Page 57: ...up the crate Power on Status At power on the module is in the following status the Output Bu er is cleared registers are set to their default con gura on A er the power on only the NIM and PLL LOCK L...

Page 58: ...So ware Tools IT IS STRONGLY SUGGESTED TO OPERATE THE DIGITIZER UPON THE STD COPY OF THE FIRMWARE UPGRADES ARE SO RECOMMENDED ONLY ON THE STD PAGE OF THE FLASH THE BKP COPY IS TO BE INTENDED ONLY FOR...

Page 59: ...the board a er a power cycle the system programs the board automa cally from the alterna ve FLASH page e g BKP FLASH page if this is not corrupted as well The user can so perform a further upgrade a e...

Page 60: ...rs area at Home Support Services describing the speci c failure A printed copy of the PRF must also be included in the package to be shipped Contacts for shipping are reported on the website at Home C...

Page 61: ...6724 User Manual rev 10 January 27th 2017 00000 00 02827 GXXX Copyright CAEN SpA All rights reserved Informa on in this publica on supersedes all earlier versions Speci ca ons subject to change withou...

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