Test Pattern Generator
The AMC FPGA can emulate the ADC and write into memory a ramp (0, 1, 2, 3,..FF, FF, FE.., 0) for test
purposes. It can be enabled via register address 0x8000.
Reset, Clear and Default Configuration
Global Reset
Global Reset is performed at power-on of the module or via so ware by write access at register address
0xEF24
. It allows to clear the data off the Output Buffer, the event counter and performs a FPGAs
global reset, which restores the FPGAs to the default configura on. It ini alizes all counters to their ini al
state and clears all detected error condi ons.
Memory Reset
The Memory Reset clears the data off the Output Buffer.
The Memory Reset can be forwarded via a write access at register address 0xEF28
.
Timer Reset
The Timer Reset allows to ini alize the mer which tags an event. The Timer Reset can be forwarded with
a pulse sent either to the GPI input (leading edge sensi ve).
UM3247 - N6724 User Manual rev. 10
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