Caen N6724, User Manual

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Clock Distribution
MUX
OSC
CLK IN
50MHz
REF-CLK
Trigger & Sync
Logic
TRG IN
LOCAL BUS
Local Bus
Interface
Acquisition
& Memory
Control
Logic
MEZZANINES (x2)
TRIGGER
SYNC
SELF-TRGs
MUX
Phase
Detector
AD9520
CLK1
Sdiv
Sdiv
Rdiv
REFIN
INTCLK
CTRL
Ldiv
Odiv
Ndiv
SAMP-CLK0
FPGA (AMC)
ADC CH1
SCLK
DATA
SYNC
SRAM
FIFO
ADC
CH0
SCLK
DATA
Ldel
Odel
Local Bus
Interface
FPGA (ROC)
SYNCB
TRG-CLK
SyncB
RAMCLK
DATA
FANOUT
OSC-CLK
SAMP-CLK1
4
DFF
VCXO
CLKOUT
CLKOUT
Fig. 7.2: Clock distribu on diagram
The clock distribu on of the module takes place on two domains: OSC-CLK and REF-CLK.
OSC-CLK is a fixed 50-MHz clock coming from a local oscillator which handles Op cal Link and Local Bus,
that takes care of the communica on between motherboard and mezzanines (see red traces in Fig.
7.2 ).
REF-CLK handles ADC sampling, trigger logic, and acquisi on logic (samples storage into RAM, buffer freez-
ing on trigger) through a clock chain. REF-CLK can be either an external (via the front panel CLK-IN connec-
tor) or an internal (via the 50-MHz local oscillator) source. In the la er mode, OSC-CLK and REF-CLK will be
synchronous (the opera on mode remains the same).
REF-CLK clock source selec on can be done by wri ng bit[6] of register 0x8100 [RD1] between the following
modes:
• INT mode (default) means REF-CLK is the 50 MHz of the local oscillator (REF-CLK = OSC-CLK);
• EXT mode means REF-CLK source is the external frequency fed on CLK-IN connector.
The external clock signal must be differen al (LVDS, ECL, PECL, LVPECL, CML) with a ji er lower than
100 ppm (see Chap.
Technical Specifica ons ). CAEN provides the A318 cable to adapt single ended signals
coming from an external clock unit into the differen al CLK-IN connector (see Tab. 1.1 ).
The N6724 is equipped with a phase-locked-loop (PLL) and clock distribu on device, AD9520. It receives
the REF-CLK and generates the sampling clock for ADCs and the mezzanine FPGA (SAMP-CLK0 and SAMP-
CLK1), as well as the trigger logic synchroniza on clock (TRG-CLK) and the output clock (CLK-OUT).
AD9520 configura on can be changed and stored into non-vola le memory. Changing the AD9520 con-
figura on is primarily intended to be used for external PLL reference clock frequency change (see Sec.
PLL
Mode ). The N6724 locks to an external 50 MHz reference clock with default AD9520 configura on.
Refer to the AD9520 datasheet for more details:
h p://www.analog.com/sta c/imported-files/data_sheets/AD9520-3.pdf
(in case the ac ve link above does not work, copy and paste it on the internet browser)
UM3247 - N6724 User Manual rev. 10 21