Decimation
This func onality is a firmware op on (AMC FPGA firmware revision
≥
0.14) based on the programmability
of a decima on factor n. During the acquisi on, the firmware processes the digi zed input waveforms
calcula ng an averaged value of the “decimated” 2
n
consecu ve samples. The self-trigger is then issued
as soon as an averaged value exceeds the programmed threshold (see Sec.
). So ware trigger
and external trigger are not affected by decima on op on.
While the real sampling frequency does not change (i.e. 100 MS/s), the decima on effect is to change
the data rate wri en into the digi zer memory. Readout data results at a sampling frequency changed
according to the formula:
100
2
n
MS/s
where n = [0, 1, , 7].
The n parameter is set through the register address 0x8044
.
Trigger Clock
The TRG-CLK logic works at 100 MHz, equal to the sampling frequency: TRG-CLK = SAMPL-CLK.
UM3247 - N6724 User Manual rev. 10
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