Caen N6724, User Manual

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Self-Trigger
Each channel can generate a self-trigger signal (SELF-TRG) when the digi zed input pulse exceeds a config-
urable threshold set through the register address 0x1n80
[RD1] . The condi on for the self-trigger genera-
on is the pulse to stay under or over the threshold (according to the trigger polarity parameter, globally
set through bit[6] of the register address 0x8000 or individually through bit[15] of register address 0x1n80)
for a number of N
th ×
4 consecu ve samples (N
th
set through the register address 0x1n84 [RD1] ). The self-
trigger is therefore delayed by N
th
quartets of samples with respect to the input signal (see Fig. 7.14 ). The
individual self-triggers from all channels are propagated to the central trigger logic on the motherboard
(see Fig.
7.13 ) where they par cipate in logic OR to produce the board common trigger, which is finally
distributed back to all channels on the mezzanines causing the event acquisi on (see Sec. Trigger distribu-
on ).
CHn_IN
THRESHOLD
Over-threshold signal from CHn
Nth [4samples] Nth [4samples] Nth [4samples]
Under-threshold signal from CHn
SELF_TRG
Fig. 7.14: Self-trigger genera on.
Bits[3:0] of register 0x810C allows the user to program which channel par cipates to the global trigger
genera on.
UM3247 - N6724 User Manual rev. 10 39