Avnet Spartan-3E, User Manual

Page: 19 / 23

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19 of 23 Rev 1.0 06/14/2006
Released Literature # ADS-005604
FX2 Signal Board net name FPGA pin Description
CTL[0] USB_CTL0 P141
CTL[1] USB_CTL1 P136
CTL[2] USB_CTL2 P120
Programmable control outputs
CTL[3] CTL3_PROG# - Output enable for FPGA_PROG# driver.
A low on this pin will drive the FPGA_PROG net.
CTL[4] CTL4_IFC_EN - Allows FX2 to drive the FPGA CCLK see schematic
pg4. Requires R16.
*Formerly connected to FPGA CS# on other Avnet
Boards.
Affected by JP4, GPIFADR[0], and IFCLK
CTL[5] FPGA_RDWR# P56 SelectMAP port read/write enable. Requires R15.
RDY[0] USB_RDY0 P139
RDY[1] USB_RDY1 P140
Sample-able ready inputs
RDY[2] FPGA_BUSY P43 SelectMAP port busy indication
RDY[3] FPGA_DONE P72 FPGA configuration DONE pin
RDY[4] FPGA_INIT# P40 FPGA initialization pin
RDY[5] USB_RDY5 - Sample-able ready input connected to JP3:15
FD[0] USB_FD0 P63
FD[1] USB_FD1 P59, P62
FD[2] USB_FD2 P58, P60
FD[3] USB_FD3 P54
FD[4] USB_FD4 P53
FD[5] USB_FD5 P52
FD[6] USB_FD6 P51
FD[7] USB_FD7 P50
Bidirectional FIFO data bus (also SMAP data)
FD0 connected to USB pins 34 and 62(DIN).
FD1&FD2 determined by JT10&JT12.
FD[8] USB_FD8 P113
FD[9] USB_FD9 P112
FD[10] USB_FD10 P106
FD[11] USB_FD11 P105
FD[12] USB_FD12 P104
FD[13] USB_FD13 P103
FD[14] USB_FD14 P98
FD[15] USB_FD15 P97
Bidirectional FIFO data bus
GPIFADR[0] USB_PC0 P71 Optional FPGA_CCLK out – See schematic sheet 4.
Affected by JP4, CTL4_IFC_EN, and IFCLK
GPIFADR[1] FPGA_M2 P57 SelectMAP port mode - M2
GPIFADR[2] FPGA_M1 P58, P60 SelectMAP port mode - M1
Connection determined by JT11.
GPIFADR[3] FPGA_M0 P59, P62 SelectMAP port mode - M0
Connection determined by JT9.
GPIFADR[4] FPGA_MOSI P44 FPGA Master Out Slave In (input to SPI Flash). May
be used to write data to SPI.
GPIFADR[5] DIN(MISO) P63 Programming input to FPGA (Data out from SPI
Flash). May be used to program FPGA or read data
from SPI.
Also connected to USB_FD0.
GPIFADR[6] FPGA_CS# P39 CS pin for SPI Flash Part
GPIFADR[7] - - No Connect
GPIFADR[8] USB_PE7 - Address output connected to JP3:16
IFCLK USB_IFCLK P126 Interface clock
PA0/INT0# USB_INT0# P135 Port A I/O or active-low interrupt 0
PA1/INT1# USB_INT1# P134 Port A I/O or active-low interrupt 1
PA2/SLOE USB_SLOE P125 Port A I/O or slave-FIFO output enable
PA3/WU2 USB_WU2 P124 Port A I/O or alternate wake-up pin
PA4/FIFOADR0 USB_FA0 P123 Port A I/O or slave-FIFO address select 0
PA5/FIFOADR1 USB_FA1 P122 Port A I/O or slave-FIFO address select 1
PA6/PKTEND USB_PEND P117 Port A I/O or slave-FIFO packet end
PA7/SLCS# USB_SLCS# P116 Port A I/O or slave-FIFO enable
RESET# USB_RESET# - Not connected to FPGA. May use JP1 to force USB
device active-low reset
CLKOUT USB_CLKOUT P128 Clock output from USB