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The Spartan-3E Evaluation board uses a dual digit 14-segment alphanumeric display from Lite-On. To enable the display,
place a jumper at JP5 position 1-2. Each segment may be controlled by the FPGA General Purpose I/O bus as listed below.
The GEN_IO 9 and 10 nets are used to drive the segment anodes, while a logic low on GEN_IO11-25 enables the individual
segments.
Display Pin#
Display Pin Name
FPGA Pin#
GEN_IO#
11 Char2
Anode P7
9
16 Char1
Anode P91
10
8 DP P8
11
17 P P88
12
13 N P14
13
2 M P87
14
4 L P15
15
5 K P86
16
6 J P16
17
14 H P82
18
15 G P26
19
18 F P85
20
1 E P20
21
7 D P83
22
9 C P21
23
10 B P81
24
12 A P22
25
Table 7 - Ethernet PHY Modes
2.9 DIP & Push-button Switches
A four-position dipswitch (SPST) has been installed on the board and attached to the FPGA. These switches provide digital
inputs to user logic as needed. The signals are pulled low (0) by 4.7K ohm resistors when the switch is open and tied to 3.3V
(1) when the switch is closed.
Switch #
Signal Name
FPGA pin#
S1-1 SWITCH0
P107
S1-2 SWITCH1
P111
S1-3 SWITCH2
P114
S1-4 SWITCH3
P119
Table 8 - DIP switch FPGA Pin-out
Two momentary closure push buttons have been installed on the board and attached to the FPGA. These buttons can be
programmed by the user and are ideal for logic reset and similar functions. Pull down resistors hold the signals low (0) until the
switch closure pulls it high (1).
Silkscreen Part #
Signal Name
FPGA pin#
SW1 SWITCH_PB1
P69
SW2 SWITCH_PB2
P66
Table 9 - Push button FPGA Pin-out
