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2.0 Hardware
This section of the manual describes the hardware of the Spartan-3E Evaluation Board. The hardware was designed with the Spartan-
3E FPGA as the focal point. The block diagram is shown in Figure 8.
Figure 3 - Spartan-3E Evaluation Kit Block Diagram
2.1 Spartan-3E
FPGA
The Spartan-3E Evaluation Board was designed to support the Spartan-3E FPGA in the 144-pin package (TQ144). This
package supports two densities 3S100E and 3S250E though initially only the 3S100E will be offered in a product. Table 2
describes the attributes of the Spartan-3E device based on density.
Spartan-
3E
System
Logic
BlockRAM
Dedicated
Max
Part
Gates
Cells
(bits)
BRAM
Multipliers
DCMs
User I/O (144
package)
XC3S100E 100K 2,160
72K
4
4
2
108
XC3S250E 250K 5,508
216K
12
12
4
108
Table 2 - Spartan-3E Attributes by Density
