Copyright © 2005 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other brands are property of their respective owners.
Avnet Electronics Marketing
13 of 23
Rev 1.0 06/14/2006
Released
Literature
#
ADS-005604
Figure 8 - USB Utility GUI
2.6 Jumper Settings
This section provides a description of the jumper settings for the Evaluation Board. The jumpers are listed in order by JP
number. The board is ready to use out of the box with the default jumper settings.
JP1 “USB RESET” – Jumper installed forces Cypress USB device into reset.
JP2 “USB EEPROM WC#” – Serial EEPROM write protect, install a shunt at position 1-2 to protect data in the upper quadrant.
For normal operation, leave shunts off or place at position 2-3. Pin is internally pulled low.
Default: Open, read/write enabled.
JP3 “USB EEPROM Unused Pins” – JP3 is actually a 10x2 header which allows user access to the Cypress EZUSBFX2 part
which are not otherwise connected on this board.
JP4 “USB CCLK ENABLE” – USB CCLK Enable, when installed enables the USB device to drive the configuration clock of the
FPGA.
Default: Open, the FPGA provides the configuration clock.
JP5 “Display Enable” – Jumper position 1-2 to enable the 2 character led segment display.
JP6 “Force JTAG Mode” – Use this jumper to enable JTAG mode. When installed, FPGA is in boundary scan mode. When
uninstalled, the FPGA will be in SPI mode.
JP7 “JTAG Par – IV”” – This is actually a connector. Use this connector when programming the device over JTAG with a
ribbon, as used with the Xilinx Parallel IV cable.
