Avnet Spartan-3E, User Manual

Page: 21 / 23

Copyright © 2005 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other brands are property of their respective owners.
Avnet Electronics Marketing
21 of 23 Rev 1.0 06/14/2006
Released Literature # ADS-005604
2.13 I/O Connectors
The Spartan-3E Evaluation Board may be populated with a 50-pin (2x25) header for access to I/Os.
2.13.1 Header “J1”
The 50-pin header labeled “J1” on the Spartan-3E Evaluation Board is connected to 47 I/O pins on the Spartan-3E
FPGA. Pin 48 on the header provides either 3.3V or 5.0V depending on the jumper pad installation on JT9 (3.3V is
the default). Note that the pins of header JP1 are shared with several other peripherals including LEDs and LED
segment display. Please see the schematic and/or other sections of this document for details.
The following table shows the pin-out for the header connector.
J1: Header 25x2
Pin FPGA Signal Signal FPGA Pin
2 P96 GEN_IO2 GEN_IO1 P2 1
4 P94 GEN_IO4 GEN_IO3 P3 3
6 P93 GEN_IO6 GEN_IO5 P4 5
8 P92 GEN_IO8 GEN_IO7 P5 7
10 P91 GEN_IO10 GEN_IO9 P7 9
12 P88 GEN_IO12 GEN_IO11 P8 11
14 P87 GEN_IO14 GEN_IO13 P14 13
16 P86 GEN_IO16 GEN_IO15 P15 15
18 P82 GEN_IO18 GEN_IO17 P16 17
20 P85 GEN_IO20 GEN_IO19 P26 19
22 P83 GEN_IO22 GEN_IO21 P20 21
24 P81 GEN_IO24 GEN_IO23 P21 23
26 P77 GEN_IO26 GEN_IO25 P22 25
28 P76 GEN_IO28 GEN_IO27 P23 27
30 P75 GEN_IO30 GEN_IO29 P25 29
32 P74 GEN_IO32 GEN_IO31 P10 31
34 P41 GEN_IO34 GEN_IO33 P32 33
36 P12 GEN_IO36 GEN_IO35 P33 35
38 P18 GEN_IO38 GEN_IO37 P34 37
40 P24 GEN_IO40 GEN_IO39 P35 39
42 P29 GEN_IO42 GEN_IO41 P132 41
44 P31 GEN_IO44 GEN_IO43 P142 43
46 P36 GEN_IO46 GEN_IO45 P38 45
48 P17 GEN_IO_CLK 3.3V/5.0V - 47
50 - Ground Ground - 49
Table 15 - Header "J1" Pin-out