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FX2 Signal

Board net name

FPGA pin

Description

SCL SCL

Serial

prom

clock

SDA SDA

Serial

prom

data

WAKEUP# USB_WAKEUP#

- USB

wakeup

signal

RXD0

USB_UART_RX0

P131

USB UART Receive

TXD0 USB_UART_TX0

P130

USB

UART

Transmit

RXD1 USB_RXD1 -

JP3,

PIN1

TXD1 USBTXD1 -

JP3,

PIN3

INT4 USB_INT4 -

JP3,

PIN5

INT5# USB_INT5# -

JP3,

PIN7

TIMER2 USB_TIMER2 -

JP3,

PIN9

TIMER1 USB_TIMER1 -

JP3,

PIN11

TIMER0 USB_TIMER0 -

JP3,

PIN13

PE0 USB_PE0

JP3,

PIN2

PE1 USB_PE1

JP3,

PIN4

PE2 USB_PE2

JP3,

PIN6

PE3 USB_PE3

JP3,

PIN8

PE4 USB_PE4

JP3,

PIN10

PE5 USB_PE5

JP3,

PIN12

PE6 USB_PE6

JP3,

PIN14

PE7 USB_PE7

JP3,

PIN16

WR# USB_WR# -

JP3,

PIN19

RD# USB_RD#

JP3,

PIN18

BKPT USB_BKPT -

JP3,

PIN17

Table 14 - USB Interface FPGA Pin-out

Summary of Contents for Spartan-3E

Page 1: ...Xilinx Spartan 3E Evaluation Kit User Guide ...

Page 2: ... 2 Character Alphanumeric LED 15 2 9 DIP Push button Switches 16 2 10 LEDs 17 2 11 Memory 17 2 11 1 SPI Flash 17 2 12 Communication RS 232 USB 2 0 18 2 12 1 RS 232 18 2 12 2 USB 2 0 18 2 13 I O Connectors 21 2 13 1 Header J1 21 2 14 Power 22 2 14 1 External AC DC Adapter J5 22 2 14 2 USB Power 22 2 14 3 TI TPS75003 22 3 0 Software BSP 22 3 1 What is included 22 3 1 1 Segment Test Project 22 4 0 Li...

Page 3: ...ttributes by Density 7 Table 3 FPGA Configuration from PROM JTAG Jumper Setting 8 Table 4 JTAG Headers Par 3 Par 4 Pin Out 8 Table 5 J6 Header SPI Pin out 11 Table 6 Available GCLK Sources 15 Table 7 Ethernet PHY Modes 16 Table 8 DIP switch FPGA Pin out 16 Table 9 Push button FPGA Pin out 16 Table 10 LED FPGA Pin out 17 Table 11 SPI FPGA Pin out 17 Table 12 RS 232 FPGA Pin out 18 Table 13 RS 232 C...

Page 4: ...he Xilinx Spartan 3E FPGA The board provides the necessary hardware to not only evaluate the features of the Spartan 3E but also to implement user applications with a basic set of peripherals Example projects are provided to help the user understand the design tool flow and leverage from known functional designs 1 2 Features FPGA Xilinx XC3S100E TQ144 Spartan 3E FPGA Board I O Connectors 50 pin he...

Page 5: ...A Cypress USB 2 0 Fly Wire Programming General Purpose I O Header JP6 U1 U2 Figure 1 Spartan 3E Evaluation Board Assembly Drawing 1 3 Demo Applications The Spartan 3E Evaluation Kit from Avnet Electronics Marketing comes with example projects designed in Xilinx ISE The example projects help the user get started by leveraging already tested and functional designs The example projects that will be d...

Page 6: ...igure 2 Spartan 3E Evaluation Board Picture 1 4 Ordering Information The following table lists the evaluation kit part numbers and available software options For more information visit the Internet link at http www em avnet com ads Part Number Hardware ADS XLX SP3E EVL100 Xilinx Spartan 3E Evaluation Kit with an XC3S100E ADS BASEX BUNDLE ISE BaseX only available with purchase of the above part num...

Page 7: ...ram is shown in Figure 8 Figure 3 Spartan 3E Evaluation Kit Block Diagram 2 1 Spartan 3E FPGA The Spartan 3E Evaluation Board was designed to support the Spartan 3E FPGA in the 144 pin package TQ144 This package supports two densities 3S100E and 3S250E though initially only the 3S100E will be offered in a product Table 2 describes the attributes of the Spartan 3E device based on density Spartan 3E...

Page 8: ...oad cable not included in the kit The Spartan 3E Evaluation Board has connectors to support both the flying leads connection of the Parallel Cable III and the ribbon cable connection of the Parallel Cable IV These connectors are labeled J4 and JP7 respectively When programming the FPGA via the JTAG interface it is good practice to place the device in Boundary Scan mode This may be accomplished usi...

Page 9: ...an3E will attempt to configure after power up by sequentially loading data from the SPI FLASH starting at address 0x0 SPI mode is selected by removing the jumper at JP6 which is the factory default The SPI FLASH is programmed via the methods discussed in section 2 4 of this manual using a HEX file as generated according to the instructions in section 2 3 2 2 3 Configuring FPGA over USB The FPGA pi...

Page 10: ...nd HEX for the format The Checksum Fill Value is the expected value in FLASH after it has been erased FF for this device The PROM File Name is the name of the file to be generated HEX will be added by the tool and location is the path to where it is to be saved These can be any valid windows expressions but avoid spaces as the Xilinx tools sometime have trouble with spaces in file names and pathwa...

Page 11: ...ailable at J6 This will allow the user to program the part via an external custom method It may be necessary when programming the SPI in this mode to place a shunt on JP9 to hold the Spartan3E PROG pin low tri stating the FPGA pins to avoid contention on the programming signals The pinout for J6 is given in the following table J6 pin Net name SPI Function FPGA Pin 1 VCC 3 3V VCC 2 FPGA_CS CS P39 3...

Page 12: ...e from the Mode drop down menu 5 Browse to or enter a filename appropriate for the selected mode a ConfigFPGA requires a BIT file b Write SPI Configuration requires a HEX file and must start at address 00000 For other options reference the Utility User Guide 6 Click the Execute button the operation doesn t start until this button is selected 7 Wait After a few seconds a progress bar will track the...

Page 13: ...quadrant For normal operation leave shunts off or place at position 2 3 Pin is internally pulled low Default Open read write enabled JP3 USB EEPROM Unused Pins JP3 is actually a 10x2 header which allows user access to the Cypress EZUSBFX2 part which are not otherwise connected on this board JP4 USB CCLK ENABLE USB CCLK Enable when installed enables the USB device to drive the configuration clock o...

Page 14: ...ure ADS 005604 JP8 SPI Flash WP A jumper on JP8 forces the devices WP signal low and places the device in write protect mode For normal operation writes enabled leave this jumper uninstalled JP9 FPGA Prog A jumper at this position will force the FPGA Prog signal low This jumper may be used to place the FPGA s pins in tri state condition Note that if HSWAP is enabled the FPGA will have internal pul...

Page 15: ... JP6 U1 U2 Figure 9 Default Jumper Placement JTx Resistor Jumpers Additional flexibility has been designed into the circuit in the form of resistor jumpers JTx and series resistors that can be moved or removed to alter the functionality of the board The purpose of some of these components may be discussed in other sections of this manual others may not be discussed at all The position of these com...

Page 16: ...16 6 J P16 17 14 H P82 18 15 G P26 19 18 F P85 20 1 E P20 21 7 D P83 22 9 C P21 23 10 B P81 24 12 A P22 25 Table 7 Ethernet PHY Modes 2 9 DIP Push button Switches A four position dipswitch SPST has been installed on the board and attached to the FPGA These switches provide digital inputs to user logic as needed The signals are pulled low 0 by 4 7K ohm resistors when the switch is open and tied to ...

Page 17: ...rtan 3E Evaluation Board is populated with a 4Mbit low voltage serial flash memory from ST Microelectronics This memory may be used to configure the S3E FPGA or to store user data 2 11 1 SPI Flash Manufacturer ST Microelectronics Part M25P40 VMN6P Attributes of the Serial Flash memory 4Mbit Up to 40MHz SPI compatible serial interface 2 7V to 3 6V operation Since the FPGA programming pins are avail...

Page 18: ...0AC The Spartan 3E Evaluation Board includes a Cypress EZ USB FX2 USB Microcontroller part number CY7C68013 100AC The EZ USB FX2 device is a single chip integrated USB 2 0 transceiver Serial Interface Engine SIE and 8051 microcontroller This device supports full speed 12 Mbps and high speed 480 Mbps modes but does not support low speed mode 1 5 Mbps The FX2 interface to the Spartan 3E FPGA is a pr...

Page 19: ...FD10 P106 FD 11 USB_FD11 P105 FD 12 USB_FD12 P104 FD 13 USB_FD13 P103 FD 14 USB_FD14 P98 FD 15 USB_FD15 P97 Bidirectional FIFO data bus GPIFADR 0 USB_PC0 P71 Optional FPGA_CCLK out See schematic sheet 4 Affected by JP4 CTL4_IFC_EN and IFCLK GPIFADR 1 FPGA_M2 P57 SelectMAP port mode M2 GPIFADR 2 FPGA_M1 P58 P60 SelectMAP port mode M1 Connection determined by JT11 GPIFADR 3 FPGA_M0 P59 P62 SelectMAP...

Page 20: ...P USB wakeup signal RXD0 USB_UART_RX0 P131 USB UART Receive TXD0 USB_UART_TX0 P130 USB UART Transmit RXD1 USB_RXD1 JP3 PIN1 TXD1 USBTXD1 JP3 PIN3 INT4 USB_INT4 JP3 PIN5 INT5 USB_INT5 JP3 PIN7 TIMER2 USB_TIMER2 JP3 PIN9 TIMER1 USB_TIMER1 JP3 PIN11 TIMER0 USB_TIMER0 JP3 PIN13 PE0 USB_PE0 JP3 PIN2 PE1 USB_PE1 JP3 PIN4 PE2 USB_PE2 JP3 PIN6 PE3 USB_PE3 JP3 PIN8 PE4 USB_PE4 JP3 PIN10 PE5 USB_PE5 JP3 PIN...

Page 21: ...her sections of this document for details The following table shows the pin out for the header connector J1 Header 25x2 Pin FPGA Signal Signal FPGA Pin 2 P96 GEN_IO2 GEN_IO1 P2 1 4 P94 GEN_IO4 GEN_IO3 P3 3 6 P93 GEN_IO6 GEN_IO5 P4 5 8 P92 GEN_IO8 GEN_IO7 P5 7 10 P91 GEN_IO10 GEN_IO9 P7 9 12 P88 GEN_IO12 GEN_IO11 P8 11 14 P87 GEN_IO14 GEN_IO13 P14 13 16 P86 GEN_IO16 GEN_IO15 P15 15 18 P82 GEN_IO18 ...

Page 22: ...le plugged into a PC or standard USB host and plug the peripheral side of the cable in to JR1 This will supply 5V to the TI voltage regulator 2 14 3 TI TPS75003 For voltage regulation the Spartan 3E Evaluation kit uses a Texas Instruments TPS75003 This is a triple supply power management IC and is designed for use with FPGAs and ASICs It features two 95 efficient buck regulators and an LDO In this...

Page 23: ... AVNET and the AV logo are registered trademarks of Avnet Inc All other brands are property of their respective owners Avnet Electronics Marketing 23 of 23 Rev 1 0 06 14 2006 Released Literature ADS 005604 4 0 List of Partners ...

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