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2.2 Configuration
The Spartan-3E Evaluation Board supports Boundary-scan (JTAG) and SPI programming methods. In addition, the user may
use the Avnet USB utility to configure the FPGA and/or SPI flash device.
Configuration Mode
(M2 : M1 : M0)
USB CCLK En
JP4
Mode Select
JP6
Notes
SPI
DEFAULT
(0:0:1)
DEFAULT
FPGA provides SPI protocol to
read from the Flash.
Boundary Scan
(1:0:1)
FPGA will
not
attempt
configuration over SPI or other
means. It may be programmed
directly over the JTAG interface.
USB
(NA)
In this mode the FPGA is
configured over USB from a
Host PC. A Windows utility is
provided.
Table 3 -
FPGA Configuration from PROM/JTAG … Jumper Setting
2.2.1 Boundary
Scan
Programming the Spartan-3E FPGA via Boundary-scan requires a JTAG download cable (not included in the kit).
The Spartan-3E Evaluation Board has connectors to support both the flying leads connection of the Parallel Cable III
and the ribbon cable connection of the Parallel Cable IV. These connectors are labeled “J4” and “JP7” respectively.
When programming the FPGA via the JTAG interface, it is good practice to place the device in Boundary Scan mode.
This may be accomplished using the Mode select jumper JP6. With JP6 off, the mode pins M[2:0] will be 001 which
enables SPI programming mode. With JP6 installed, the mode pins M[2:0] will be 101 which enables boundary scan
mode. Note that power should be removed when changing the programming Mode.
For Boundary Scan mode, place
a jumper at JP6
Figure 4 - Boundary Scan Mode Selection via JP6
JTAG Header (J4)
J4 is a 6x1 standard 0.1” header and is intended for use with flying leads, such as those of the Xilinx Parallel Cable 3
(PC3) downloading/debugging cable. Connect the leads as indicated in Table 4 below for “J4” as demonstrated in
Figure 5.
Signal Name
Par-3 (J4) pin
PAR-4 Ribbon (JP7) pin
VCC 1
2
TDI 2
10
TDO 3
8
TMS 5
4
TCK 4
6
GND 6
1,3,5,7,9,11 or 13
Table 4 -
JTAG Headers (Par-3 & Par-4) Pin-Out