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2.12 Communication (RS-232, USB 2.0)
For communication, the Spartan-3E FPGA has access to an RS232 transceiver and a USB2.0 transceiver.
2.12.1 RS-232
Manufacturer: Harris/Intersil
Part #: ICL3222CA
The RS-232 transceiver is a 3222 available from Harris/Intersil (ICL3222CA) and Analog Devices (ADM3222). This
transceiver is operating at 3.3V for VCC. The internal charge pump creates the RS232 compatible output levels.
The standard RX and TX lines (pin3 and pin2) are connected to the FPGA by way of the 3222. Please see the table
below for the FPGA pin-out.
A straight through serial cable should be used to plug “J3” into a standard PC serial port (male DB9).
Signal Name
FPGA pin#
Xcvr pin#
Note
(from FPGA perspective)
Transmit (RS232_TX1)
P67
13
Out to DB9-2
Receive (RS232_ RX1)
P47
15
In from DB9-3
CTS (RS232_ CTS)
P68
12
Out to DB9-8
RTS (RS232_ RTS)
P48
10
In from DB9-7
Table 12 - RS-232 FPGA Pin-out
Signal Name
DB9 J3
Xcvr pin#
TX 2
17
RX 3
16
CTS 8 8
RTS 7 9
GND 5 -
Table 13 - RS-232 Connector Pin-out
2.12.2 USB
2.0
Manufacturer: Cypress
Part #: CY7C68013-100AC
The Spartan-3E Evaluation Board includes a Cypress EZ-USB FX2™ USB Microcontroller, part number CY7C68013-
100AC. The EZ-USB FX2 device is a single-chip integrated USB 2.0 transceiver, Serial Interface Engine (SIE) and
8051 microcontroller. This device supports full-speed (12 Mbps) and high-speed (480 Mbps) modes, but does not
support low-speed mode (1.5 Mbps). The FX2 interface to the Spartan-3E FPGA is a programmable state machine
that supports 8- or 16-bit parallel data transfers. This interface is called the General Programmable Interface (GPIF).
The GPIF is controlled by Waveform Descriptors that are created with the Cypress “GPIFTool” utility and downloaded
to the FX2 over the USB cable. The GPIF descriptors are stored in internal RAM and are loaded by the firmware
during initialization. The GPIF interface is made up of the signals in the following table, which are connected to
Spartan-3E FPGA.
Some of the additional GPIF pins are connected to the configuration port on the Spartan-3E FPGA. This provides for
the development of a FPGA configuration tool, which may be created by Avnet at a later date. The pins which will
affect FPGA configuration are shaded in the following table.
The USB FX2 device can also be used in a slave mode where the FPGA accesses the FX2 like a FIFO. For more
information about the FX2 modes of operation, see the “EZ-USB FX2 Technical Reference Manual” and the FX2
datasheet available on Cypress Semiconductor’s web site (
http://www.cypress.com
).
