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ATtiny26(L)
1477G–AVR–03/05
ware when executing the corresponding interrupt handling vector. Alternatively, OCF1B
is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the
I-bit in SREG, OCIE1B, and OCF1B are set (one), the Timer/Counter1 B Compare
Match interrupt is executed.
• Bits 4..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
• Bit 2 – TOV1: Timer/Counter1 Overflow Flag
The bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV1 is cleared, after synchronization clock cycle, by writing a logical one to the flag.
When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and
TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed.
• Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logical one to the flag. When the SREG I-bit, and TOIE0
(T i me r/Co un ter 0 Ov erflo w Inte rru pt E n ab le ), a nd T OV 0 are s et (o ne ), th e
Timer/Counter0 Overflow interrupt is executed.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
