Atmel ATtiny26 Manual Download Page 151

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ATtiny26(L)

1477G–AVR–03/05

Figure 110. I/O Pin Input Threshold Voltage vs. V

, I/O Pin Read as “0”)

Figure 111. I/O Pin Input Hysteresis vs. V

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

VIL, IO PIN READ AS '0'

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I/O PIN INPUT HYSTERESIS vs. V

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0.5

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85°C

25°C

-40°C

Summary of Contents for ATtiny26

Page 1: ...tion Detector 10 bit ADC 11 Single Ended Channels 8 Differential ADC Channels 7 Differential ADC Channel Pairs with Programmable Gain 1x 20x On chip Analog Comparator External Interrupt Pin Change Int...

Page 2: ...0 T0 PB6 ADC10 RESET PB7 PA0 ADC0 PA1 ADC1 PA2 ADC2 PA3 AREF GND AVCC PA4 ADC3 PA5 ADC4 PA6 ADC5 AIN0 PA7 ADC6 AIN1 PDIP SOIC 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12...

Page 3: ...r mostats and firedetectors among other applications The ATtiny26 L provides 2K bytes of Flash 128 bytes EEPROM 128 bytes SRAM up to 16 general purpose I O lines 32 general purpose working registers t...

Page 4: ...TROL TIMER COUNTER1 MCU STATUS REGISTER PORT A DRIVERS PA0 PA7 VCC GND ANALOG COMPARATOR 8 BIT DATA BUS ADC ISP INTERFACE INTERRUPT UNIT EEPROM INTERNAL OSCILLATOR OSCILLATORS CALIBRATED OSCILLATOR IN...

Page 5: ...sed as the reset To use pin PB7 as an I O pin instead of RESET pin program 0 RSTDISBL Fuse Port B has alternate functions for the ADC clocking timer counters USI SPI programming and pin change interru...

Page 6: ...executed in the ALU Figure 2 shows the ATtiny26 L AVR Enhanced RISC microcontroller architecture In addition to the register operation the conventional memory addressing modes can be used on the Regi...

Page 7: ...ared in the linker file Refer to the C user guide for more information The 128 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture The...

Page 8: ...lexibility in access of the registers as the X Y and Z registers can be set to index any register in the file X register Y register and Z register The registers R26 R31 have some added functions to th...

Page 9: ...in a register in the Register File by the BLD instruction Bit 5 H Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations See the Instruction Set Description for de...

Page 10: ...Pointer is incremented by one when data is popped from the Stack with the POP instruction and it is incremented by two when an address is popped from the Stack with return from subroutine RET or retu...

Page 11: ...are contained in register r Rr and d Rd The result is stored in register d Rd I O Direct Figure 7 I O Direct Addressing Operand address is contained in 6 bits of the instruction word n is the destinat...

Page 12: ...esult of the Y or Z register contents added to the address con tained in 6 bits of the instruction word Data Indirect Figure 10 Data Indirect Addressing Operand address is the contents of the X Y or t...

Page 13: ...or Z register is incremented after the operation Operand address is the con tent of the X Y or Z register prior to incrementing Constant Addressing Using the LPM Instruction Figure 13 Code Memory Con...

Page 14: ...n continues at address contained by the Z register i e the PC is loaded with the contents of the Z register Relative Program Addressing RJMP and RCALL Figure 15 Relative Program Memory Addressing Prog...

Page 15: ...unit Figure 16 The Parallel Instruction Fetches and Instruction Executions Figure 17 shows the internal timing concept for the Register File In a single clock cycle an ALU operation using two register...

Page 16: ...on Flash data downloading See Program and Data Addressing Modes on page 10 for the different program memory addressing modes Figure 19 SRAM Organization SRAM Data Memory Figure 19 above shows how the...

Page 17: ...rase cycles per location EEPROM Read Write Access The EEPROM Access Registers are accessible in the I O space The write access time is typically 8 3 ms A self timing function lets the user software de...

Page 18: ...ss and data are correctly set up the EEWE bit must be set to write the value in to the EEPROM The EEMWE bit must be set when the logical one is written to EEWE otherwise no EEPROM write takes place Th...

Page 19: ...tion During periods of low VCC the EEPROM data can be corrupted because the supply volt age is too low for the CPU and the EEPROM to operate properly These issues are the same as for board level syste...

Page 20: ...Register B 2E 4E TCNT1 Timer Counter1 8 bit 2D 4D OCR1A Timer Counter1 Output Compare Register A 2C 4C OCR1B Timer Counter1 Output Compare Register B 2B 4B OCR1C Timer Counter1 Output Compare Register...

Page 21: ...range 00 1F are directly bit accessible using the SBI and CBI instructions In these registers the value of single bits can be checked by using the SBIS and SBIC instruc tions Refer to the instruction...

Page 22: ...ck clkI O The I O clock is used by the majority of the I O modules like Timer Counters and USI The I O clock is also used by the External Interrupt module but note that some external interrupts are de...

Page 23: ...However even if the pos sibly divided RC Oscillator is taken to a higher frequency than 1 MHz the fast peripheral clock frequency saturates at 70 MHz worst case and remains oscillating at the maxi mu...

Page 24: ...for Table 3 Device Clocking Options Select Device Clocking Option PLLCK CKSEL3 0 External Crystal Ceramic Resonator 1 1111 1010 External Low frequency Crystal 1 1001 External RC Oscillator 1 1000 010...

Page 25: ...option C1 and C2 should always be equal The optimal value of the capacitors depends on the crystal or resonator in use the amount of stray capacitance and the electromag netic noise of the environmen...

Page 26: ...capacitors The internal capacitors have a nomi nal value of 36 pF When this oscillator is selected start up times are determined by the SUT Fuses as shown in Table 8 Note 1 These options should only b...

Page 27: ...perating mode is selected by the fuses CKSEL3 0 as shown in Table 9 When this oscillator is selected start up times are determined by the SUT Fuses as shown in Table 10 Notes 1 This option should not...

Page 28: ...PB4 XTAL1 and PB5 XTAL2 can be used as general I O ports Note 1 The device is shipped with this option selected Oscillator Calibration Register OSCCAL Bits 7 0 CAL7 0 Oscillator Calibration Value Writ...

Page 29: ...XTAL1 and GND Figure 24 External Clock Drive Configuration When this clock source is selected start up times are determined by the SUT Fuses as shown in Table 14 When applying an external clock it is...

Page 30: ...L3 0 must be set to 0001 This clocking option can be used only when operating between 4 5 5 5V to guaratee safe operation The system clock frequency will be 16 MHz 64 MHz 4 When using this clock optio...

Page 31: ...VCC is below the Brown out Reset threshold VBOT During reset all I O Registers are then set to their initial values and the program starts execution from address 000 The instruction placed in address...

Page 32: ...tivated whenever VCC is below the detection level The POR circuit can be used to trigger the Start up Reset as well as detect a failure in supply voltage The Power on Reset POR circuit ensures that th...

Page 33: ...e a reset even if the clock is not running Shorter pulses are not guaranteed to generate a reset When the applied signal reaches the Reset Threshold Voltage VRST on its positive edge the delay timer s...

Page 34: ...trigger level for the BOD can be selected by the fuse BODLEVEL to be 2 7V BODLEVEL unprogrammed or 4 0V BODLEVEL programmed The trigger level has a hysteresis of 50 mV to ensure spike free Brown out D...

Page 35: ...External Reset Flag This bit is set one if an External Reset occurs The bit is reset zero by a Power on Reset or by writing a logic zero to the flag Bit 0 PORF Power on Reset Flag This bit is set one...

Page 36: ...lpful in selecting an appropriate sleep mode MCU Control Register MCUCR The MCU Control Register contains control bits for general MCU functions Bits 7 Res Reserved Bit This bit is a reserved bit in t...

Page 37: ...to continue operating if enabled This sleep mode basically halts clkI O clkCPU and clkFLASH while allowing the other clocks to run This improves the noise environment for the ADC enabling higher reso...

Page 38: ...ock option is selected the SLEEP instruction forces the MCU into the Standby mode This mode is identical to Power down with the exception that the Oscillator is kept running From Standby mode the devi...

Page 39: ...leep modes this will contribute significantly to the total current consumption Refer to Brown out Detection on page 34 for details on how to configure the Brown out Detector Internal Voltage Reference...

Page 40: ...40 ATtiny26 L 1477G AVR 03 05 and the input signal is left floating or have an analog signal level close to VCC 2 the input buffer will use excessive power...

Page 41: ...the register or bit defines in a program the precise form must be used For example PORTB3 for bit no 3 in Port B here documented generally as PORTxn The physical I O Registers and bit locations are li...

Page 42: ...hen the pin is configured as an input pin the pull up resistor is activated To switch the pull up resistor off PORTxn has to be written logic zero or the pin has to be configured as an output pin The...

Page 43: ...a timing diagram of the synchronization when reading an externally applied pin value The maximum and minimum propagation delays are denoted tpd max and tpd min respectively Figure 33 Synchronization w...

Page 44: ...ue a nop instruction must be inserted as indicated in Figure 34 The out instruction sets the SYNC LATCH signal at the positive edge of the clock In this case the delay tpd through the synchronizer is...

Page 45: ...ting or have an analog signal level close to VCC 2 SLEEP is overridden for port pins enabled as External Interrupt pins If the External Interrupt Request is not enabled SLEEP is active also for these...

Page 46: ...32 can be overrid den by alternate functions The overriding signals may not be present in all port pins but the figure serves as a generic description applicable to all port pins in the AVR micro cont...

Page 47: ...lue If DDOE is set the Output Driver is enabled disabled when DDOV is set cleared regardless of the setting of the DDxn Register bit PVOE Port Value Override Enable If this signal is set and the Outpu...

Page 48: ...are changes on PA7 PA6 and PA3 digital inputs PA3 output and pullup driver are also overridden ADC6 AIN1 Port A Bit 7 AIN1 Analog Comparator Negative input and ADC6 ADC input channel 6 Configure the...

Page 49: ...to digital converter AREF PCINT1 Port A Bit 3 AREF External Reference for ADC Pullup and output driver are disabled on PA3 when the pin is used as an external reference or Internal Voltage Reference...

Page 50: ...escribed in Pin Change Interrupt on page 62 2 Not operator is marked with Table 25 Overriding Signals for Alternate Functions in PA3 PA0 Signal Name PA3 AREF PCINT1 PA2 ADC2 PA1 ADC1 PA0 ADC0 PUOE ADM...

Page 51: ...r RESET External Reset input is active low and enabled by unprogramming 1 the RSTDISBL Fuse Pullup is activated and output driver and digital input are deactivated when the pin is used as the RESET pi...

Page 52: ...digital port function from interfering with the function of the ana log to digital converter XTAL2 Chip Clock Oscillator pin 2 Used as clock pin for all chip clock sources except internal calibrateble...

Page 53: ...o be configured as an output DDB2 set one to serve this function PCINT1 Pin Change Interrupt 0 pin Pin change interrupt is enabled on pin when global interrupt is enabled pin change interrupt is enabl...

Page 54: ...se active low is described in section System Control and Reset on page 31 2 Note that the PCINT1 Interrupt is only enabled if both the Global Interrupt Flag is enabled the PCIE1 flag in GIMSK is set a...

Page 55: ...peration is described in Universal Serial Interface USI on page 80 7 Operation of the data pin SDA in USI Two wire mode and DI in USI Three wire mode in Universal Serial Interface USI on page 80 8 Not...

Page 56: ...A Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 19 39 PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA Read Write R R R R R R R R Initial Value N A N...

Page 57: ...ents 000 rjmp RESET Reset handler 001 rjmp EXT_INT0 IRQ0 handler 002 rjmp PIN_CHANGE Pin change handler 003 rjmp TIM1_CMP1A Timer1 compare match 1A 004 rjmp TIM1_CMP1B Timer1 compare match 1B 005 rjmp...

Page 58: ...hen returning from an interrupt routine This must be handled by software Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum After...

Page 59: ...s Reserved Bit This bit is a reserved bit in the ATtiny26 L and always reads as zero Bit 6 INTF0 External Interrupt Flag0 When an event on the INT0 pin triggers an interrupt request INTF0 becomes set...

Page 60: ...the Timer Counter Interrupt Flag Register TIFR Bit 1 TOIE0 Timer Counter0 Overflow Interrupt Enable When the TOIE0 bit is set one and the I bit in the Status Register is set one the Timer Counter0 Ove...

Page 61: ...g interrupt handling vector Alternatively TOV1 is cleared after synchronization clock cycle by writing a logical one to the flag When the SREG I bit and TOIE1 Timer Counter1 Overflow Interrupt Enable...

Page 62: ...B 3 0 The pin change interrupt is different from other interrupts in two ways First pin change interrupt enable bits PCIE1 and PCIE0 also mask the flag if they are not set The normal operation on most...

Page 63: ...hree wire mode TC1 compare PWM USICR USIWM1 USICR USIWM1 USIWM0 TCCR1A COM1A1 COM1A0 PWM1A 1 01 011 PB1 USI Three wire mode TC1 compare PWM USICR USIWM1 USIWM0 TCCR1A COM1A1 TCCR1A COM1A0 01 1 1 PB2 U...

Page 64: ...synchronous mode uses the system clock CK as the clock timebase and asynchronous mode uses the fast peripheral clock PCK as the clock time base Timer Counter0 Prescaler Figure 36 below shows the Time...

Page 65: ...er TIFR Control signals are found in the Timer Counter0 Control Register TCCR0 The interrupt enable disable settings for Timer Counter0 are found in the Timer Counter Interrupt Mask Register TIMSK Whe...

Page 66: ...tion is performed Writing a zero to this bit will have no effect This bit will always be read as zero Bits 2 1 0 CS02 CS01 CS00 Clock Select0 Bit 2 1 and 0 The Clock Select0 bits 2 1 and 0 define the...

Page 67: ...o modes Figure 39 shows Timer Counter1 synchronization register block dia gram and synchronization delays in between registers Note that all clock gating details are not shown in the figure The Timer...

Page 68: ...nous Timer Counter1 needs at least two edges of the PCK when the system clock is high If the frequency of the system clock is too high it is a risk that data or control val ues are lost The following...

Page 69: ...normal mode In PWM mode OCR1A and OCR1B provide the data values against which the Timer Counter value is compared Upon compare match the PWM outputs OC1A OC1A OC1B OC1B are generated In PWM mode the T...

Page 70: ...Refer to Table 35 on page 75 for a detailed description Bit 3 FOC1A Force Output Compare Match 1A Writing a logical one to this bit forces a change in the Compare Match output pin PB1 OC1A according t...

Page 71: ...h Modulator B Enable When set one this bit enables PWM mode based on comparator OCR1B in Timer Counter1 and the counter value is reset to 00 in the CPU clock cycle after a compare match with OCR1C Reg...

Page 72: ...ains data to be continuously com pared with Timer Counter1 Actions on compare matches are specified in TCCR1A A compare match does only occur if Timer Counter1 counts to the OCR1A value A soft Table 3...

Page 73: ...lue A software write that sets TCNT1 and OCR1C to the same value does not generate a compare match If the CTC1 bit in TCCR1B is set a compare match will clear TCNT1 and set an Over flow Interrupt Flag...

Page 74: ...OC1A and OC1B OC1B are never both set at the same time This allows driving power switches directly The non overlap time is one prescaled clock cycle and the high time is one cycle shorter than the lo...

Page 75: ...read out of OCR1A or OCR1B When OCR1A or OCR1B contain 00 or the top value as specified in OCR1C Register the output PB1 OC1A or PB3 OC1B is held low or high according to the settings of COM1A1 COM1A0...

Page 76: ...tput Compare flags and interrupts The frequency of the PWM will be Timer Clock 1 Frequency divided by OCR1C value 1 See the following equation Resolution shows how many bit is required to express the...

Page 77: ...K 8 0100 132 7 1 70 PCK 4 0011 228 7 8 80 PCK 4 0011 199 7 6 90 PCK 4 0011 177 7 5 100 PCK 4 0011 159 7 3 110 PCK 4 0011 144 7 2 120 PCK 4 0011 132 7 1 130 PCK 2 0010 245 7 9 140 PCK 2 0010 228 7 8 15...

Page 78: ...egister for details Figure 43 Watchdog Timer Watchdog Timer Control Register WDTCR Bits 7 5 Res Reserved Bits These bits are reserved bits in the ATtiny26 L and will always read as zero Bit 4 WDCE Wat...

Page 79: ...of the Watchdog Oscillator is voltage dependent The WDR Watch dog Reset instruction should always be executed before the Watchdog Timer is enabled This ensures that the reset period will be in accorda...

Page 80: ...arent latch is inserted between the serial register output and output pin which delays the change of data out put to the opposite clock edge of the data input sampling The serial input is always sampl...

Page 81: ...from the Shift Register USI Status Register USISR The Status Register contains interrupt flags line status flags and the counter value Note that doing a Read Modify Write operation on USISR Register...

Page 82: ...his feature is enabled by write a one to the USICLK bit while setting an external clock source USICS1 1 Note that even when no wire mode is selected USIWM1 0 0 the external clock input SCK SCL are can...

Page 83: ...controlled by the PORTB1 bit The Data Input DI and Serial Clock SCK pins do not affect the normal port operation When operating as master clock pulses are software generated by toggling the PORTB2 bit...

Page 84: ...ifted into the Shift Register is sampled the previous instruction cycle The bit will be read as zero When an external clock source is selected USICS1 1 the USICLK function is changed from a clock stro...

Page 85: ...ter Overflow interrupt flag or USIOIF can therefore be used to determine when a transfer is completed The clock is generated by the master device software by toggling the PB2 pin via the PORTB Registe...

Page 86: ...counter will count both edges 3 Step 2 is repeated eight times for a comlpete register byte transfer 4 After eight clock pulses i e 16 clock edges the counter will overflow and indi cate that the tra...

Page 87: ...SICR r16 out USICR r17 out USICR r16 LSB out USICR r17 in r16 USIDR ret SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI slave init ldi r16 1 USIWM0 1 USI...

Page 88: ...mas ter and slave operation at this level is the serial clock generation which is always done by the master and only the slave uses the clock control unit Clock generation must be implemented in soft...

Page 89: ...ve edge of the SCL clock 4 After eight bits are transferred containing slave address and data direction read or write the slave counter overflows and the SCL line is forced low D If the slave is not t...

Page 90: ...r to the description of Bit 7 USISIF Start Condition Interrupt Flag on page 81 for further details Alternative USI Usage When the USI unit is not used for serial communication it can be set up to do a...

Page 91: ...ontrol and Status Register ACSR Bit 7 ACD Analog Comparator Disable When this bit is set one the power to the Analog Comparator is switched off This bit can be set at any time to turn off the Analog C...

Page 92: ...bit is set one and the ADC is switched off ADEN in ADCSR is zero MUX3 0 in ADMUX select the input pin to replace the negative input to the Analog Comparator as shown in Table 42 on page 93 If ACME is...

Page 93: ...nalog Comparator 3 The MUX3 0 selections go into effect after one clock cycle delay Table 42 Analog Comparator Input Selection 1 ACME ADEN MUX3 0 3 Analog Comparator Negative Input 0 X XXXX AIN1 1 1 X...

Page 94: ...ns from Port B Seven of the differential inputs are equipped with a program mable gain stage providing amplification steps of 0 dB 1x and 26 dB 20x on the differential input voltage before the A D con...

Page 95: ...single ended inputs to the ADC A selection of ADC input pins can be selected as positive and negative inputs to the differential gain amplifier If differential channels are selected the differential g...

Page 96: ...l is selected while a conversion is in progress the ADC will finish the current conversion before performing the channel change The ADC generates a 10 bit result which is presented in the ADC Data Reg...

Page 97: ...gain stage may take as much as 125 s to stabilize to the new value Thus conversions should not be started within the first 125 s after selecting a new differential channel Alternatively conversions r...

Page 98: ...clock cycle before the conversion completes ADIF in ADCSR is set Note that the con version starts on the following rising ADC clock edge after ADSC is written The user is thus advised not to write new...

Page 99: ...enabled ADEN 1 ADSC 0 ADFR 0 ADIE 1 2 Enter ADC Noise Reduction mode or Idle mode The ADC will start a conver sion once the CPU has been halted 3 If no other interrupts occur before the ADC conversion...

Page 100: ...ADCL will thus read 0x00 and ADCH will read 0xC8 Writing zero to ADLAR right adjusts the result ADCL 0x20 ADCH 0x03 Table 44 Correlation Between Input Voltage and Output Codes VADCn Read code Correspo...

Page 101: ...ight adjusted If ADLAR is set the result is left adjusted Changing the ADLAR bit will affect the ADC Data Register immediately regardless of any ongoing conversions For a complete description of this...

Page 102: ...00101 ADC5 00110 ADC6 00111 ADC7 01000 ADC8 01001 ADC9 01010 ADC10 01011 N A ADC0 ADC1 20x 01100 ADC0 ADC1 1x 01101 1 ADC1 ADC1 20x 01110 ADC2 ADC1 20x 01111 ADC2 ADC1 1x 10000 N A ADC2 ADC3 1x 10001...

Page 103: ...igh until the real conversion completes Writing a 0 to this bit has no effect Bit 5 ADFR ADC Free Running Select When this bit is set one the ADC operates in Free Running mode In this mode the ADC sam...

Page 104: ...rsion Result These bits represent the result from the conversion For differential channels this is the absolute value after gain adjustment as indicated in Table 46 on page 102 For single ended channe...

Page 105: ...ll analog components in the application should have a separate analog ground plane on the PCB This ground plane is connected to the digital ground plane via a single point on the PCB 2 Keep analog sig...

Page 106: ...9 INT0 T0 PB6 ADC8 XTAL2 PB5 ADC7 XTAL1 PB4 VCC PA1 ADC1 PA2 ADC2 PA3 AREF PA4 ADC3 PA5 ADC4 PA6 ADC5 AIN0 PA7 ADC6 AIN1 GND AVCC 10 100nF Analog Ground Plane ATtiny26 L 20 20 6 5 7 8 9 GND 10 16 14 1...

Page 107: ...Bit No Description Default Value 7 1 unprogrammed 6 1 unprogrammed 5 1 unprogrammed 4 1 unprogrammed 3 1 unprogrammed 2 1 unprogrammed LB2 1 Lock bit 1 unprogrammed LB1 0 Lock bit 1 unprogrammed Table...

Page 108: ...Note that the Fuse bits are locked if Lock bit1 LB1 is programmed Program the Fuse bits before programming the Lock bits Table 50 Fuse High Byte Fuse High Byte Bit No Description Default Value 7 1 unp...

Page 109: ...o the OSCCAL Register If other frequencies are used the calibration value has to be loaded manually see Oscillator Calibration Register OSC CAL on page 28 for details Page Size Parallel Programming Pa...

Page 110: ...lexed with Byte Select 2 0 selects low byte 1 selects 2 nd high byte PAGEL BS1 1 PB3 I Program Memory and EEPROM data Page Load multiplexed with Byte Select 1 0 selects low byte 1 selects high byte OE...

Page 111: ...XA1 and XA0 Coding 1 XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address High or low address byte determined by BS1 0 1 Load Data High or Low data byte for Flash determined by BS1 1...

Page 112: ...age 110 to 0000 2 Apply 4 5 5 5V between VCC and GND simultanously as 11 5 12 5V is applied to RESET 3 Wait 100 ns 4 Re program the fuses to ensure that External Clock is selected as clock source CKSE...

Page 113: ...oad Command Write Flash 1 Set XA1 XA0 to 10 This enables command loading 2 Set BS1 to 0 3 Set DATA to 0001 0000 This is the command for Write Flash 4 Give XTAL1 a positive pulse This loads the command...

Page 114: ...forms H Repeat B through G until the entire Flash is programmed or until all data has been programmed I End Page Programming 1 Set XA1 XA0 to 10 This enables command loading 2 Set DATA to 0000 0000 Th...

Page 115: ...memory is as follows refer to Programming the Flash on page 113 for details on Command Address and Data loading 1 A Load Command 0001 0001 2 B Load Address Low Byte 00 FF 3 C Load Data 00 FF J Repeat...

Page 116: ...the EEPROM memory is as follows refer to Programming the Flash on page 113 for details on Command and Address loading 1 A Load Command 0000 0011 2 B Load Address Low Byte 00 FF 3 Set OE to 0 and BS1...

Page 117: ...ing 1 A Load Command 0010 0000 2 C Load Data Low Byte Bit n 0 programs the Lock bit 3 Give WR a negative pulse and wait for RDY BSY to go high The Lock bits can only be cleared by executing Chip Erase...

Page 118: ...4 Set OE to 1 Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows refer to Programming the Flash for details on Command and Address loading 1 A Load Command 0000...

Page 119: ...rements Note 1 The timing requirements shown in Figure 64 i e tDVXH tXHXL and tXLDX also apply to reading operation XTAL1 PAGEL BS1 XLXH t ADDR0 Low Byte DATA Low Byte DATA High Byte ADDR1 Low Byte DA...

Page 120: ...ntrol Valid before XTAL1 High 67 ns tXLXH XTAL1 Low to XTAL1 High 200 ns tXHXL XTAL1 Pulse Width High 150 ns tXLDX Data and Control Hold after XTAL1 Low 67 ns tXLWL XTAL1 Low to WR Low 0 ns tWLBX BS2...

Page 121: ...d by the internal oscillator there is no need to connect a clock source to the XTAL1 pin 2 VCC 0 3V AVCC VCC 0 3V however AVCC should always be within 2 7 5 5V When programming the EEPROM an auto eras...

Page 122: ...w Programming Enable command 4 The Flash is programmed one page at a time The page size is found in Table 52 on page 109 The memory page is loaded one byte at a time by supplying the 4 LSB of the addr...

Page 123: ...d is being programmed into EEPROM reading the address location being programmed will give the value FF At the time the device is ready for a new byte the programmed value will read correctly This is u...

Page 124: ...d data o from EEPROM memory at address b Write EEPROM Memory 1100 0000 xxxx xxxx xbbb bbbb iiii iiii Write data i to EEPROM memory at address b Read Lock Bits 0101 1000 0000 0000 xxxx xxxx xxxx xxoo R...

Page 125: ...Parameter Min Typ Max Units 1 tCLCL Oscillator Frequency VCC 2 7 5 5 V 0 8 MHz tCLCL Oscillator Period VCC 2 7 5 5 V 125 ns 1 tCLCL Oscillator Frequency VCC 4 5 5 5 V 0 16 MHz tCLCL Oscillator Period...

Page 126: ...0 mA TA 40 C to 85 C VCC 2 7V to 5 5V unless otherwise noted Symbol Parameter Condition Min Typ 1 Max Units VIL Input Low Voltage Except XTAL1 pin and RESET pins 0 5 0 2VCC V VIH Input High Voltage E...

Page 127: ...nt the following must be observed 1 The sum of all IOH for all ports should not exceed 400 mA 2 The sum of all IOH for port A0 A7 should not exceed 300 mA 3 The sum of all IOH for ports B0 B7 should n...

Page 128: ...he frequency will vary with package type and board layout VIL1 VIH1 Table 63 External Clock Drive Symbol Parameter VCC 2 7 5 5V VCC 4 5 5 5V Units Min Max Min Max 1 tCLCL Oscillator Frequency 0 8 0 16...

Page 129: ...nded Conversion VREF 4V VCC 4V ADC clock 1 MHz Noise Reduction mode 2 LSB Integral Non Linearity INL Single Ended Conversion VREF 4V VCC 4V ADC clock 200 kHz 0 5 LSB Differential Non Linearity DNL Sin...

Page 130: ...Error Gain 1x VREF 4V VCC 5V ADC clock 50 200 kHz 1 5 LSB Gain 20x VREF 4V VCC 5V ADC clock 50 200 kHz 2 LSB Gain Error Gain 1x 2 Gain 20x 2 5 Offset Error Gain 1x VREF 4V VCC 5V ADC clock 50 200 kHz...

Page 131: ...e operating voltage and frequency The current drawn from capacitive loaded pins may be estimated for one pin as CL VCC f where CL load capacitance VCC operating voltage and f average switch ing freque...

Page 132: ...nt vs VCC Internal RC Oscillator 8 MHz ACTIVE SUPPLY CURRENT vs FREQUENCY 1 20 MHz 0 5 10 15 20 25 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 5 5V 4 5V 4 0V 3 3V 2 7V 3 0V 5 0V ACTIVE SUPPLY CU...

Page 133: ...Supply Current vs VCC Internal RC Oscillator 2 MHz ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 4 MHz 0 1 2 3 4 5 6 7 8 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C ACTIVE SUPPLY CURREN...

Page 134: ...77 Active Supply Current vs VCC PLL Oscillator ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 1 MHz 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C ACTIVE...

Page 135: ...Supply Current vs Frequency 0 1 1 0 MHz ACTIVE SUPPLY CURRENT vs VCC 32kHz EXTERNAL OSCILLATOR 0 10 20 30 40 50 60 70 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 25 C IDLE SUPPLY CURRENT vs FREQUENCY 0...

Page 136: ...rent vs VCC Internal RC Oscillator 8 MHz IDLE SUPPLY CURRENT vs FREQUENCY 1 20 MHz 0 2 4 6 8 10 12 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 5 5V 4 5V 4 0V 3 3V 2 7V 3 0V 5 0V IDLE SUPPLY CURR...

Page 137: ...Current vs VCC Internal RC Oscillator 2 MHz IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 4 MHz 0 0 5 1 1 5 2 2 5 3 3 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C IDLE SUPPLY CURRENT vs...

Page 138: ...ure 85 Idle Supply Current vs VCC PLL Oscillator IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 1 MHz 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C IDLE SUP...

Page 139: ...ure 87 Power down Supply Current vs VCC Watchdog Timer Disabled IDLE SUPPLY CURRENT vs VCC 32kHz EXTERNAL OSCILLATOR 0 5 10 15 20 25 30 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 25 C POWER DOWN SUPPLY CUR...

Page 140: ...y Supply Current vs VCC 455 kHz Resonator Watchdog Timer Disabled POWER DOWN SUPPLY CURRENT vs VCC WATCHDOG TIMER ENABLED 0 2 4 6 8 10 12 14 16 18 20 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40...

Page 141: ...by Supply Current vs VCC 2 MHz Resonator Watchdog Timer Disabled STANDBY SUPPLY CURRENT vs VCC 1 MHz RESONATOR WATCHDOG TIMER DISABLED 0 10 20 30 40 50 60 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA STANDBY...

Page 142: ...Supply Current vs VCC 4 MHz Resonator Watchdog Timer Disabled STANDBY SUPPLY CURRENT vs VCC 2 MHz XTAL WATCHDOG TIMER DISABLED 0 10 20 30 40 50 60 70 80 90 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA STANDB...

Page 143: ...Supply Current vs VCC 6 MHz Resonator Watchdog Timer Disabled STANDBY SUPPLY CURRENT vs VCC 4 MHz XTAL WATCHDOG TIMER DISABLED 0 20 40 60 80 100 120 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA STANDBY SUPPL...

Page 144: ...7 I O Pin Pull up Resistor Current vs Input Voltage VCC 5V STANDBY SUPPLY CURRENT vs VCC 6 MHz XTAL WATCHDOG TIMER DISABLED 0 20 40 60 80 100 120 140 160 180 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA I O...

Page 145: ...Reset Pull up Resistor Current vs Reset Pin Voltage VCC 5V I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE Vcc 2 7V 0 10 20 30 40 50 60 70 80 0 0 5 1 1 5 2 2 5 3 VOP V I OP uA 85 C 25 C 40 C RESET...

Page 146: ...ength Figure 101 I O Pin Source Current vs Output Voltage VCC 5V RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE Vcc 2 7V 0 10 20 30 40 50 60 0 0 5 1 1 5 2 2 5 3 VRESET V I RESET uA 40 C 25 C 85 C...

Page 147: ...gure 103 I O Pin Sink Current vs Output Voltage VCC 5V I O PIN SOURCE CURRENT vs OUTPUT VOLTAGE Vcc 2 7V 0 5 10 15 20 25 30 0 0 5 1 1 5 2 2 5 3 VOH V I OH mA 85 C 25 C 40 C I O PIN SINK CURRENT vs OUT...

Page 148: ...Reset Pin as I O Source Current vs Output Voltage VCC 5V I O PIN SINK CURRENT vs OUTPUT VOLTAGE Vcc 2 7V 0 5 10 15 20 25 30 35 0 0 5 1 1 5 2 2 5 VOL V I OL mA 85 C 25 C 40 C RESET PIN AS I O SOURCE C...

Page 149: ...7 Reset Pin as I O Sink Current vs Output Voltage VCC 5V RESET PIN AS I O SOURCE CURRENT vs OUTPUT VOLTAGE Vcc 2 7V 0 0 5 1 1 5 2 2 5 0 0 5 1 1 5 2 2 5 3 VOH V Current mA 85 C 25 C 40 C RESET PIN AS I...

Page 150: ...109 I O Pin Input Threshold Voltage vs VCC VIH I O Pin Read as 1 RESET PIN AS I O SINK CURRENT vs OUTPUT VOLTAGE Vcc 2 7V 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 0 0 5 1 1 5 2 2 5 VOL V Current mA 85 C 25 C 40...

Page 151: ...as 0 Figure 111 I O Pin Input Hysteresis vs VCC I O PIN INPUT THRESHOLD VOLTAGE vs VCC VIL IO PIN READ AS 0 0 0 5 1 1 5 2 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C I O PIN INPUT HYSTERE...

Page 152: ...ut Threshold Voltage vs VCC VIL Reset Pin Read as 0 RESET PIN AS I O INPUT THRESHOLD VOLTAGE vs VCC VIH RESET PIN READ AS 1 0 0 5 1 1 5 2 2 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C R...

Page 153: ...hold Voltage vs VCC VIH Reset Pin Read as 1 RESET PIN AS I O PIN HYSTERESIS vs VCC 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C RESET INPUT THRESHOLD VOLTAGE...

Page 154: ...17 Reset Input Pin Hysteresis vs VCC RESET INPUT THRESHOLD VOLTAGE vs VCC VIL RESET PIN READ AS 0 0 0 5 1 1 5 2 2 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C RESET INPUT PIN HYSTERESIS...

Page 155: ...Temperature BOD Level is 2 7V BOD THRESHOLDS vs TEMPERATURE BODLEVEL IS 4 0V 3 8 3 9 4 4 1 4 2 4 3 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature C Threshold V Rising VCC Falling VCC BOD...

Page 156: ...0V BANDGAP vs VCC 1 216 1 218 1 22 1 222 1 224 1 226 1 228 1 23 1 232 1 234 1 236 2 5 3 3 5 4 4 5 5 5 5 Vcc V Bandgap Voltage V 85 C 25 C 40 C ANALOG COMPARATOR OFFSET VOLTAGE vs COMMON MODE VOLTAGE...

Page 157: ...llator Frequency vs VCC ANALOG COMPARATOR OFFSET VOLTAGE vs COMMON MODE VOLTAGE Vcc 2 7V 0 0 001 0 002 0 003 0 004 0 005 0 006 0 007 0 008 0 009 0 0 5 1 1 5 2 2 5 3 Common Mode Voltage V Comparator Of...

Page 158: ...25 Calibrated 8 MHz RC Oscillator Frequency vs VCC CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 6 4 6 9 7 4 7 9 8 4 8 9 60 40 20 0 20 40 60 80 100 Ta C F RC MHz 5 0V 3 5V 2 7V CALIBRATED 8MH...

Page 159: ...requency vs Temperature CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE 3 5 5 5 7 5 9 5 11 5 13 5 15 5 17 5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE F RC MHz CALIBR...

Page 160: ...quency vs Osccal Value CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs VCC 3 4 3 5 3 6 3 7 3 8 3 9 4 4 1 4 2 4 3 4 4 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz 85 C 25 C 40 C CALIBRATED 4MHz RC OSCILLATOR FREQ...

Page 161: ...RC Oscillator Frequency vs VCC CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 1 75 1 8 1 85 1 9 1 95 2 2 05 2 1 2 15 60 40 20 0 20 40 60 80 100 Ta C F RC MHz 5 0V 3 5V 2 7V CALIBRATED 2MHz RC...

Page 162: ...Frequency vs Temperature CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE 0 8 1 3 1 8 2 3 2 8 3 3 3 8 4 3 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE F RC MHz CALIBRAT...

Page 163: ...llator Frequency vs Osccal Value CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs VCC 0 85 0 9 0 95 1 1 05 1 1 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz 85 C 25 C 40 C CALIBRATED 1MHz RC OSCILLATOR FREQUENCY v...

Page 164: ...etector Current vs VCC Figure 137 ADC Current vs VCC AREF AVCC BROWNOUT DETECTOR CURRENT vs VCC 0 0 005 0 01 0 015 0 02 0 025 0 03 0 035 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 25 C 85 C 40 C ADC CURREN...

Page 165: ...vs VCC Figure 139 Analog Comparator Current vs VCC AREF EXTERNAL REFERENCE CURRENT vs VCC 0 50 100 150 200 250 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C ANALOG COMPARATOR CURRENT vs VCC 0...

Page 166: ...CC 0 1 1 0 MHz Excluding Current Through The Reset Pull up PROGRAMMING CURRENT vs VCC 0 1 2 3 4 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C RESET SUPPLY CURRENT vs VCC 0 1 1 0 MHz EXCLUDING...

Page 167: ...Figure 143 Reset Pulsewidth vs VCC RESET SUPPLY CURRENT vs VCC 1 20 MHz EXCLUDING CURRENT THROUGH THE RESET PULLUP 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 5 5V 4...

Page 168: ...rved 23 43 Reserved 22 42 Reserved 21 41 WDTCR WDCE WDE WDP2 WDP1 WDP0 78 20 40 Reserved 1F 3F Reserved 1E 3E EEAR EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 17 1D 3D EEDR EEPROM Data Register 8 Bit 18...

Page 169: ...K Compare Register with Immediate Rd K Z N V C H 1 SBRC Rr b Skip if Bit in Register Cleared if Rr b 0 PC PC 2 or 3 None 1 2 3 SBRS Rr b Skip if Bit in Register is Set if Rr b 1 PC PC 2 or 3 None 1 2...

Page 170: ...ster from Stack Rd STACK None 2 BIT AND BIT TEST INSTRUCTIONS SBI P b Set Bit in I O Register I O P b 1 None 2 CBI P b Clear Bit in I O Register I O P b 0 None 2 LSL Rd Logical Shift Left Rd n 1 Rd n...

Page 171: ...ATtiny26L 8MC 20P3 20S 32M1 A Commercial 0 C to 70 C ATtiny26L 8PI ATtiny26L 8SI ATtiny26L 8MI ATtiny26L 8PU 2 ATtiny26L 8SU 2 ATtiny26L 8MU 2 20P3 20S 32M1 A 20P3 20S 32M1 A Industrial 40 C to 85 C 1...

Page 172: ...ANE A D e eB eC COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX NOTE A 5 334 A1 0 381 D 25 493 25 984 Note 2 E 7 620 8 255 E1 6 096 7 112 Note 2 B 0 356 0 559 B1 1 270 1 551 L 2 921 3 810 C 0...

Page 173: ...imension D does not include mold Flash protrusions or gate burrs Mold Flash protrusions and gate burrs shall not exceed 0 15 mm 0 006 per side 3 Dimension E does not include inter lead Flash or protru...

Page 174: ...NSIONS Unit of Measure mm SYMBOL MIN NOM MAX NOTE D1 D E1 E e b A3 A2 A1 A D2 E2 0 08 C L 1 2 3 P P 0 1 2 3 A 0 80 0 90 1 00 A1 0 02 0 05 A2 0 65 1 00 A3 0 20 REF b 0 18 0 23 0 30 D 5 00 BSC D1 4 75 B...

Page 175: ...175 ATtiny26 L 1477G AVR 03 05 Errata ATtiny26 all revisions No errata...

Page 176: ...in the datasheet Changes from Rev 1477D 05 03 to Rev 1477E 10 03 1 Removed Preliminary references 2 Updated Features on page 1 3 Removed SSOP package reference from Pin Configuration on page 2 4 Upda...

Page 177: ...added Table 66 ADC Char acteristics Differential Channels TA 40 C to 85 C on page 130 13 Updated ATtiny26 Typical Characteristics on page 131 14 Added LPM Rd Z and LPM Rd Z in Instruction Set Summary...

Page 178: ...SRAM Data Memory 16 EEPROM Data Memory 17 I O Memory 20 System Clock and Clock Options 22 Clock Systems and their Distribution 22 Clock Sources 24 Default Clock Source 25 Crystal Oscillator 25 Low fr...

Page 179: ...ounter1 Prescaler 65 8 bit Timer Counter0 65 8 bit Timer Counter1 67 Watchdog Timer 78 Universal Serial Interface USI 80 Overview 80 Register Descriptions 81 Functional Descriptions 85 Alternative USI...

Page 180: ...DC Characteristics 129 ATtiny26 Typical Characteristics 131 Register Summary 168 Instruction Set Summary 169 Ordering Information 171 Packaging Information 172 20P3 172 20S 173 32M1 A 174 Errata 175 A...

Page 181: ...iv ATtiny26 L 1477G AVR 03 05...

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