98
ATtiny26(L)
1477G–AVR–03/05
Figure 54. ADC Timing Diagram, Single Conversion
Figure 55. ADC Timing Diagram, Free Running Conversion
Changing Channel or
Reference Selection
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a tem-
porary register to which the CPU has random access. This ensures that the channels
and reference selection only takes place at a safe point during the conversion. The
channel and reference selection is continuously updated until a conversion is started.
Once the conversion starts, the channel and reference selection is locked to ensure a
sufficient sampling time for the ADC. Continuous updating resumes in the last ADC
clock cycle before the conversion completes (ADIF in ADCSR is set). Note that the con-
version starts on the following rising ADC clock edge after ADSC is written. The user is
thus advised not to write new channel or reference selection values to ADMUX until one
ADC clock cycle after ADSC is written.
Table 43. ADC Conversion Time
Condition
Sample & Hold (Cycles from
Start of Conversion)
Conversion
Time (Cycles)
Conversion
Time (µs)
Extended conversion
13.5
25
125 - 500
Normal conversions
1.5
13
65 - 260
1
2
3
4
5
6
7
8
9
10
11
12
13
MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
1
2
One Conversion
Next Conversion
3
Sample & Hold
MUX and REFS
Update
Conversion
Complete
MUX and REFS
Update
11
12
13
MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
1
2
One Conversion
Next Conversion
3
4
Conversion
Complete
Sample & Hold
MUX and REFS
Update
