30
ATtiny26(L)
1477G–AVR–03/05
High Frequency PLL
Clock – PLL
CLK
There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC
Oscillator for the use of the Peripheral Timer/Counter1 and for the system clock source.
When selected as a system clock source, by programming (“0”) the fuse PLLCK, it is
divided by four. When this option is used, the CKSEL3..0 must be set to “0001”. This
clocking option can be used only when operating between 4.5 - 5.5V to guaratee safe
operation. The system clock frequency will be 16 MHz (64 MHz/4). When using this
clock option, start-up times are determined by the SUT Fuses as shown in Table 15.
See also “PCK Clocking System” on page 23.
Table 15. Start-up Times for the PLLCK
SUT1..0
Start-up Time from
Power-down
Additional Delay from
Reset (V
CC
= 5.0V)
Recommended Usage
00
1K CK
–
BOD enabled
01
1K CK
4.1 ms
Fast rising power
10
1K CK
65 ms
Slowly rising power
11
16K CK
–
Slowly rising power
