68
ATtiny26(L)
1477G–AVR–03/05
Figure 39. Timer/Counter1 Synchronization Register Block Diagram
Timer/Counter1 and the prescaler allow running the CPU from any clock source while
the prescaler is operating on the fast 64 MHz PCK clock in the asynchronous mode.
Note that the system clock frequency must be lower than one half of the PCK frequency.
Only when the system clock is generated from PCK dividing that by two, the ratio of the
PCK/system clock can be exactly two. The synchronization mechanism of the asynchro-
nous Timer/Counter1 needs at least two edges of the PCK when the system clock is
high. If the frequency of the system clock is too high, it is a risk that data or control val-
ues are lost.
The following Figure 40 shows the block diagram for Timer/Counter1.
O C R 1 A
8 -B IT D A T A B U S
S Y N C
M O D E
1 C K d e la y
T C N T 1
C K
O C F 1 A
O C F 1 B
T C N T 1
T O V 1
O C R 1 B
O C R 1 C
T C C R 1 A
T C C R 1 B
O C R 1 A _ S I
O C R 1 B _ S I
O C R 1 C _ S I
T C C R 1 A _ S I
T C C R 1 B _ S I
T C N T 1
O C F 1 A
O C F 1 B
T O V 1
T C N T 1 _ S I
O C F 1 A _ S I
O C F 1 B _ S I
T O V 1 _ S I
T C N T _ S O
O C F 1 A _ S O
O C F 1 B _ S O
T O V 1 _ S O
S
A
A S Y N C
M O D E
1 P C K d e lay
1 /2 P C K -1 C K d e la y
1 /2 P C K -1 C K d e la y
P C K
P C K E
S
A
S
A
S
A
S
A
S
A
n o d e la y
n o d e la y
IO -re g is te rs
In p u t sy n c ro n iz a tio n
re g is te rs
T im e r/C o u n te r1
O u tp u t
m u ltip lex e rs
O u tp u t
s y nc ro n iz atio n
re g is te rs
