177
ATtiny26(L)
1477G–AVR–03/05
4.
Added section “Default Clock Source” on page 25.
5.
Corrected PLL Lock value in the “Bit 0 – PLOCK: PLL Lock Detector” on page
74.
6.
Added information about conversion time when selecting differential chan-
nels on page 97.
7.
Corrected {DDxn, PORTxn} value on page 43.
8.
Added section “Unconnected Pins” on page 46.
9.
Added note for RSTDISBL Fuse in Table 50 on page 108.
10. Corrected DATA value in Figure 61 on page 116.
11. Added WD_FUSE period in Table 60 on page 123.
12. Updated “ADC Characteristics” on page 129 and added Table 66, “ADC Char-
acteristics, Differential Channels, T
13. Updated “ATtiny26 Typical Characteristics” on page 131.
14. Added LPM Rd, Z and LPM Rd, Z+ in “Instruction Set Summary” on page 169.
Changes from Rev.
1477B-04/02 to Rev.
1477C-09/02
1.
Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.
Changes from Rev.
1477A-03/02 to Rev.
1477B-04/02
1.
Removed all references to Power Save sleep mode in the section “System
Clock and Clock Options” on page 22.
2.
Updated the section “Analog to Digital Converter” on page 94 with more
details on how to read the conversion result for both differential and single-
ended conversion.
3.
Updated “Ordering Information” on page 171 and added QFN/MLF package
information.
