99
ATtiny26(L)
1477G–AVR–03/05
Special care should be taken when changing differential channels. Once a differential
channel has been selected, the gain stage may take as much as 125 µs to stabilize to
the new value. Thus conversions should not be started within the first 125 µs after
selecting a new differential channel. Alternatively, conversion results obtained within this
period should be discarded.
The same settling time should be observed for the first differential conversion after
changing ADC reference (by changing the REFS1:0 bits in ADMUX).
ADC Noise Canceler
Function
The ADC features a noise canceler that enables conversion during ADC Noise Reduc-
tion mode (see “Power Management and Sleep Modes” on page 36) to reduce noise
induced from the CPU core and other I/O peripherals. If other I/O peripherals must be
active during conversion, this mode works equivalently for Idle mode. To make use of
this feature, the following procedure should be used:
1.
Make sure that the ADC is enabled and is not busy converting. Single Conver-
sion mode must be selected and the ADC conversion complete interrupt must be
enabled.
ADEN = 1
ADSC = 0
ADFR = 0
ADIE = 1
2.
Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conver-
sion once the CPU has been halted.
3.
If no other interrupts occur before the ADC conversion completes, the ADC inter-
rupt will wake up the CPU and execute the ADC Conversion Complete interrupt
routine.
ADC Conversion Result
After the conversion is complete (ADIF is high), the conversion result can be found in
the ADC Result Registers (ADCL, ADCH).
For single ended conversion, the result is
where V
IN
is the voltage on the selected input pin and V
REF
the selected voltage refer-
ence (see Table 45 on page 101 and Table 46 on page 102). 0x000 represents analog
ground, and 0x3FF represents the selected reference voltage minus one LSB.
If differential channels are used, the result is
where V
POS
is the voltage on the positive input pin, V
NEG
the voltage on the negative
input pin, GAIN the selected gain factor, and V
REF
the selected voltage reference. Keep
in mind that V
POS
must be higher than V
NEG
, otherwise, the ADC value will saturate at
0x000. Figure 56 shows the decoding of the differential input range.
Table 44 shows the resulting output codes if the differential input channel pair (ADCn -
ADCm) is selected with a gain of GAIN and a reference voltage of V
REF
.
ADC
V
IN
1024
⋅
V
REF
--------------------------
=
ADC
V
POS
V
NEG
–
(
)
GAIN
1024
⋅
⋅
V
REF
---------------------------------------------------------------------------
=
