[AKD4671-B]
<KM089001>
2008
/
03
-
9
-
(2) External Master Mode
The AK4671 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock can be input
via MCKI pin, without using on-chip PLL circuit. The clock required to operate is MCKI (256fs, 384fs, 512fs,
768fs or 1024fs). The input frequency of MCKI is selected by FS1-0 bits.
AK4671
DSP or
μ
P
MCKI
BICK
LRCK
SDTO
SDTI
BCLK
LRCK
SDTI
SDTO
MCKO
1fs
32fs or 64fs
MCLK
256fs, 384fs, 512fs,
768fs or 1024fs
(2-1)
Evaluation of A/D using DIT of AK4114
X2 (X’tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP).
In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 19.
The jumper pins should be set as the following.
(2-2) Evaluation of D/A using DIR of AK4114
PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT4 (DSP).
In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 19.
The jumper pins should be set as the following.
JP36
MCLK
DIR
EXT
JP35
PHASE
INV
THR
JP38
LRCK_SEL
4040
DIR
4040
DIR
JP33
BICK_SEL
JP46
4114_MCKI
JP48
M/S
Slave
Master
JP36
MCLK
DIR
EXT
JP35
PHASE
INV
THR
JP38
LRCK_SEL
4040
DIR
JP51
SDTI_SEL
ADC
DIR
JP33
BICK_SEL
4040
DIR
JP48
M/S
Slave
Master
