ASAHI AKD4671-B Manual Download Page 42

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DVDD

AVDD

ROUTN

ROUTP

LOUT1

ROUT1

LOUT2

ROUT2

LOUT3

ROUT3

4670_SAVDD

HPR

HPL

SCL

SDA

PDN

LOUTN

LOUTP

SVDD

SAIN1 SAIN2 SAIN3

4670_TVDD3

4670_MCKO

4670_SDTO

4670_MCKI

4670_SDTI

4670_BICK

4670_LRCK

AVDD

4670_AVDD

4670_PDN

4670_I2C

CCLK/SCL

CSN/CAD0

CDTI/SDA

4670_CDTO

4670_DVDD

4670_SDTOA

4670_SDTIA

SPLIN

SPRIN

DVDD

SDA

4670_PVDD

4670_TVDD2

RIN1

LIN1

RIN2

LIN2

RIN3

LIN3

RIN4

LIN4

4670_SYNCB

4670_SDTOB

4670_SDTIB

4670_BICKB

4670_SYNCA

4670_BICKA

Title

Size

Document Number

Rev

Date:

Sheet

AK4671

AKD4671-B

Wednesday, March 26, 2008

Title

Size

Document Number

Rev

Date:

Sheet

AK4671

AKD4671-B

Wednesday, March 26, 2008

Title

Size

Document Number

Rev

Date:

Sheet

AK4671

AKD4671-B

Wednesday, March 26, 2008

GND

MPWR

(NMT)

TP46

AVDD

TP46

AVDD

10u

C23
10u

2.2k

R17

0.1u

TP25

LOUTN

TP25

LOUTN

JP3LIN2

C29

0.033u

C29

0.033u

JP8

SDA

JP8

SDA

TP16

LOUT2

TP16

LOUT2

C34

0.015u

C34

0.015u

JP7

MCKO

JP7

MCKO

TP34

TEST

TP34

TEST

TP61

BICKB

TP61

BICKB

TP33

GPO2

TP33

GPO2

C26

0.22u

C26

0.22u

C12

10u

C12

10u

TP3
LIN2

TP36

MCKO

TP36

MCKO

R16

TP13

ROUT1

TP13

ROUT1

TP6
RIN3

JP13

U2 LIN1

JP13

U2 LIN1

C35

0.1u

C35

0.1u

TP26

VSS3

TP26

VSS3

TP49

BICK

TP49

BICK

TP32

SPRIN

TP32

SPRIN

R22

2.2u

2.2k

JP1

RIN2

JP1

RIN2

C17

10u

C17

10u

R11

TP52

CSN

TP52

CSN

TP1
LIN1

C38

2.2u

C38

2.2u

C18

0.1u

C18

0.1u

R15

JP10

TVDD

JP10

TVDD

AK4671

MDT

MPWR

SAIN3

SAIN2

SAIN1

SAVDD

VSS3

TVDD3

SDTOB

SYNCB

BICKB

SDTI

GPO1

CDTO

SDTO

PDN

LRCK

MCKI

MCKO

I2C

BICK

CSN/CAD0

DVDD

CDTI/SDA

GPO2

SDTIA

BICKA

SYNCA

SDTOA

TVDD2

VSS2

PVDD

VCOCBT

VCOM

MUTET

ROUT2

LOUT2

TEST

AVDD

VSS1

ROUT1/RCN

LOUT1/RCP

ROUT3/LON

LOUT3/LOP

SDTIB

CCLK/SCL

VSS4

VCOC

LIN2/IN2+

RIN2/IN2-

LIN3/IN3+

RIN3/IN3-

LIN4/IN4+

RIN4/IN4-

LIN1/IN1+

RIN1/IN1-

TP60

SDTIB

TP60

SDTIB

TP64

BICKA

TP64

BICKA

C13
0.1u

CN1

80pin_1

CN1

80pin_1

CN4

80pin_4

CN4

80pin_4

TP51

PDN

TP51

PDN

TP39

SDTI

TP39

SDTI

2.2k

TP65

SDTOA

TP65

SDTOA

TP21

HPR

TP21

HPR

R12

R25

TP20

VCOCBT

TP20

VCOCBT

TP14

PVDD

TP14

PVDD

C27

0.22u

C27

0.22u

TP4
RIN2

C24

0.1u

C24

0.1u

TP54

CDTI

TP54

CDTI

(NMT)

AK4212

(NMT)

AK4212

MIXR

SPRIN

AVDD

AVSS

TVDD

CCLK/SCL

CDTI/SDA

PDN

PVDD

PVEE

HPL

HPR

RIN4/IN4+

LIN4/IN4-

RIN3/IN3+

LIN3/IN3-

VREF

RIN2/IN2+

LIN2/IN2-

RIN1/IN1+

ROUTP

SVDD

SVSS

LOUTP

LOUTN

MIXL

SPLIN

PVSS

LIN1/IN1-

ROUTN

C10

2.2u

C10

2.2u

TP5
LIN3

TP41

MDT

TP41

MDT

R30

TP8
RIN4

TP56

ROUTN

TP56

ROUTN

JP15

U2 SPLIN

JP15

U2 SPLIN

C22

0.1u

C22

0.1u

C11

(open)

C11

(open)

TP40

MPWR

TP40

MPWR

R23

C39

10u

C39

10u

TP59

SDTOB

TP59

SDTOB

R10

TP30

VSS4

TP30

VSS4

TP2
RIN1

2.2k

C20

0.1u

C20

0.1u

R24

TP38

SPLIN

TP38

SPLIN

R13

R19

220k

R19

220k

C31

0.1u

C31

0.1u

TP28

TVDD2

TP28

TVDD2

TP44

VCOM

TP44

VCOM

TP27

TVDD3

TP27

TVDD3

R28

10k

R27

10k

R27

10k

JP14

U2 SPRIN

JP14

U2 SPRIN

TP18

LOUT3

TP18

LOUT3

TP29

LOUTP

TP29

LOUTP

C19

10u

C19

10u

TP50

I2C

TP50

I2C

TP15

ROUT2

TP15

ROUT2

C25

10u

C25

10u

CN3

80pin_3

CN3

80pin_3

TP58

SYNCB

TP58

SYNCB

JP2LIN1

TP11
SAIN3

C15

0.1u

C15

0.1u

C37

0.033u

C37

0.033u

TP48

LRCK

TP48

LRCK

TP62

SDTIA

TP62

SDTIA

TP7
LIN4

R29

C28

0.015u

C28

0.015u

open

10u

R14

JP5

PVDD

JP5

PVDD

R21

TP43

VCOC

TP43

VCOC

R26

TP19

ROUT3

TP19

ROUT3

TP53

CCLK

TP53

CCLK

TP10
SAIN2

TP24

SAVDD

TP24

SAVDD

R18

C14

2.2u

C14

2.2u

C16

0.1u

C16

0.1u

JP11

AVDD

JP11

AVDD

C21

10u

C21

10u

TP57

ROUTP

TP57

ROUTP

4.7n

R31

TP55

CDTO

TP55

CDTO

TP17

VSS2

TP17

VSS2

TP9
SAIN1

TP42

MCKI

TP42

MCKI

TP31

GPO1

TP31

GPO1

TP47

SVDD

TP47

SVDD

C36

0.1u

C36

0.1u

R20

TP63

SYNCA

TP63

SYNCA

TP35

SDTO

TP35

SDTO

0.1u

TP37

DVDD

TP37

DVDD

TP23

HPL

TP23

HPL

JP12

U2 RIN1

JP12

U2 RIN1

C33

10u

C33

10u

JP6

PDN

JP6

PDN

JP4

RIN1

JP4

RIN1

JP9

SCL

JP9

SCL

TP45
VSS1

TP12

LOUT1

TP12

LOUT1

C40

4.7n

C40

4.7n

CN2

TP22

MUTET

TP22

MUTET

Summary of Contents for AKD4671-B

Page 1: ...software are packed with this This control software does not support Windows NT FUNCTION DIT DIR with optical input output 10pin Header for Digital Audio I F PCM I F Baseband Bluetooth BNC connector f...

Page 2: ...from ROUT pin J5 It is analog signal input Jack The signal is input to LIN2 or LIN3 or LIN4 pins and JP23 should be selected J7 It is analog signal input Jack The signal is input to RIN2 or RIN3 or R...

Page 3: ...T4 The clock and data of DSP can be inputted and outputted with this connector PORT6 The clock and data of Bluetooth mode can be inputted and outputted with this connector 7 PORT1 PORT2 Optical Connec...

Page 4: ...open 3 3V supplied PVDD Orange 2 2 3 6V PVDD for AK4671 Default open typ 3 3V open 3 3V supplied DVDD Orange 1 6 3 6V DVDD for AK4671 Default open typ 3 3V open 3 3V supplied TVDD2 Orange 1 6 3 6V TVD...

Page 5: ...3 3V TVDD2 Orange 1 6 3 6V TVDD2 for AK4671 Default should be connected typ 3 3V 3 3V TVDD3 Orange 1 6 3 6V TVDD3 for AK4671 Default should be connected typ 3 3V 3 3V VCC Orange 1 6 3 6V for logic De...

Page 6: ...s fed externally BICK and LRCK are divided with a board 1 5 All interface signals including master clock are fed externally 2 External Master Mode 2 1 Evaluation of A D using DIT of AK4114 2 2 Evaluat...

Page 7: ...1 DSP or P MCKI BICK LRCK SDTO SDTI BCLK LRCK SDTI SDTO MCKO 1fs 32fs MCLK 256fs 384fs 512fs 768fs or 1024fs 1 1 Evaluation of A D using DIT of AK4114 X2 X tal and PORT2 DIT are used Nothing should be...

Page 8: ...according to the frequency of MCLK BICK and LRCK Follows are setting examples in MCLK 256fs BICK 64fs and LRCK 1fs When MCLK 384fs or 768fs JP32 JP34 and JP37 should be set to 384 side 1 5 All interf...

Page 9: ...used Nothing should be connected to PORT1 DIR and PORT4 DSP In Master Mode BICK and LRCK of AK4671 should be input to AK4114 Please refer to Table 2 on page 19 The jumper pins should be set as the fol...

Page 10: ...2 4 All interface signals including master clock are fed externally PORT4 DSP is used Nothing should be connected to PORT1 DIR and PORT2 DIT The jumper pins should be set as the following JP36 MCLK DI...

Page 11: ...quency can be selected by FS3 0 bits 3 1 PLL Reference Clock MCKI pin AK4671 DSP or P MCKO BICK LRCK SDTO SDTI BCLK LRCK SDTI SDTO MCKI 1fs 32fs MCLK 256fs 128fs 64fs 32fs 11 2896MHz 12MHz 12 288MHz 1...

Page 12: ...en 3 1 3 All interface signals including master clock are fed externally PORT4 DSP is used Nothing should be connected to PORT1 DIR and PORT2 DIT The jumper pins should be set as the following JP36 MC...

Page 13: ...P MCKI BICK LRCK SDTO SDTI BCLK LRCK SDTI SDTO MCKO 1fs 32fs PLL Reference Clock LRCK pin 3 2 1 Evaluation of A D using DIT of AK4114 X2 X tal and PORT2 DIT are used Nothing should be connected to PO...

Page 14: ...master clock are fed externally PORT4 DSP is used Nothing should be connected to PORT1 DIR and PORT2 DIT The jumper pins should be set as the following JP36 MCLK JP33 BICK_SEL 4040 DIR DIR EXT JP38 LR...

Page 15: ...CK SDTI SDTO MCKI 1fs 32fs 64fs 256fs 128fs 64fs 32fs 11 2896MHz 12MHz 12 288MHz 13MHz 13 5MHz 19 2MHz 24MHz 26MHz 27MHz MCLK 4 1 Evaluation of A D using DIT of AK4114 J12 EXT and PORT2 DIT are used N...

Page 16: ...4 3 All interface signals including master clock are fed externally PORT4 DSP is used Nothing should be connected to PORT1 DIR and PORT2 DIT The jumper pins should be set as the following JP36 MCLK J...

Page 17: ...ut clock frequency of BICKA or BICKB pin AK4671 does not support master mode for both PCM I F A and B nor slave mode for both PCM I F A and B When PMPCM bit is 0 SYNCA BICKA SYNCB and BICKB pins are H...

Page 18: ...lock SYNCA or BICKA pin 1 1 SYNCA and BICKA are fed from on board clock generator X1 X tal PORT3 Baseband Module and PORT6 Bluetooth Module are used The jumper pins should be set as the following Plea...

Page 19: ...odule PORT3 Baseband Module and PORT6 Bluetooth Module are used SYNCA and BICKA should be supplied from PORT3 The jumper pins should be set as the following JP47 BICKA PHASE is jumper which decides po...

Page 20: ...lock SYNCB or BICKB pin 2 1 SYNCB and BICKB are fed from on board clock generator X1 X tal PORT3 Baseband Module and PORT6 Bluetooth Module are used The jumper pins should be set as the following Plea...

Page 21: ...h Module PORT3 Baseband Module and PORT6 Bluetooth Module are used Please supply SYNCB and BICKB from PORT6 The jumper pins should be set as the following JP54 BICKB PHASE is jumper which decides pola...

Page 22: ...eft justified 16bit Right justified H L O 64fs O 0 0 1 24bit Left justified 18bit Right justified H L O 64fs O 0 1 0 24bit Left justified 20bit Right justified H L O 64fs O 0 1 1 24bit Left justified...

Page 23: ...Default JP4 RIN1 RIN1 input GND In case of full differential input MPWR MIC power is supplied to RIN1 OPEN MIC power is not supplied to RIN1 Default JP7 MCKO MCKO output SHORT When AK4671 outputs MCK...

Page 24: ...lel port of IBM AT compatible PC Connect PORT5 CTRL with PC by 10 wire flat cable packed with the AKD4671 Table 4 shows switch and jumper settings for serial control I2C Mode should be selected in Tab...

Page 25: ..._SEL LIN2 RIN1 C50 1u R39 short 1 2 3 4 5 J5 LIN LIN1 LIN4 LIN3 Figure 4 LIN1 RIN1 LIN2 RIN2 LIN3 RIN3 and LIN4 RIN4 Input Circuit LIN2 RIN2 LIN3 RIN3 and LIN4 RIN4 share J5 J7 JP23 LIN_SEL and JP25 R...

Page 26: ...UT2 ROUT3 ROUT1 ROUT3 LOUT1 JP21 ROUT_SEL ROUT2 1 2 3 J3 HP ROUT1 R36 16 JP58 L_16ohm 1 2 3 4 5 J1 LOUT C47 100u R37 short JP59 R_16ohm JP17 HPL JACK JP16 LOUT_SEL JP19 HPR JACK Figure 6 LOUT1 ROUT1 L...

Page 27: ...am according to explanation above 2 Click Port Reset button 3 Click Write default button Explanation of each buttons Port Reset Set up the USB interface board AKDUSBIF A Write default Initialize the r...

Page 28: ...4671 click OK button If not click Cancel button 3 Function2 Dialog Dialog to evaluate DATT Address Box Input registers address in 2 figures of hexadecimal Start Data Box Input starts data in 2 figures...

Page 29: ...file name is akr Operation flow 1 Click Save Button 2 Set the file name and push Save Button The extension of file name is akr 4 2 Open The register setting data saved by Save is written to AK4671 Th...

Page 30: ...val time Set 1 to the address of the step where the sequence should be paused 3 Click Start button Then this sequence is executed The sequence is paused at the step of Interval 1 Click START button th...

Page 31: ...1 B KM089001 2008 03 31 6 Function4 Dialog The sequence that is created on Function3 can be assigned to buttons and executed When F4 button is clicked the window as shown in Figure 9 opens Figure 8 F4...

Page 32: ...cuted 6 2 SAVE and OPEN buttons on right side SAVE The sequence file names can assign be saved The file name is ak4 OPEN The sequence file names assign that are saved in ak4 are loaded 6 3 Note 1 This...

Page 33: ...ns and executed When F5 button is clicked the following window as shown in Figure 11 opens Figure 10 F5 window 7 1 OPEN buttons on left side and WRITE button 1 Click OPEN button and select the registe...

Page 34: ...n can be saved The file name is ak5 OPEN The register setting file names assign that are saved in ak5 are loaded 7 3 Note 1 All files need to be in same folder used by SAVE and OPEN function on right...

Page 35: ...easily set the AK4671 s programmable filter A calculation of a coefficient of Digital Programmable Filter such as HPF EQ filter a write to a register and check frequency response Window to show to Fig...

Page 36: ...e Frequency fs 10000 Pole Frequency 0 497 fs Zero point Frequency Zero point Frequency fs 10000 Zero point Frequency 0 497 fs Gain Gain 0dB Gain 12dB 5 Band Equalizer EQ1 5 Center Frequency EQ1 5 Cent...

Page 37: ...displayed and a calculation of register setting is not executed Figure14 A register setting calculation result In the following cases a register set values are updated 1 When Register Setting button w...

Page 38: ...n Notch Filter Auto Correction 8 4 Automatic compensation for center frequency of a notch filter When a gain of 5 band Equalizer is set to 1 Equalizer becomes a notch filter When center frequency of s...

Page 39: ...uency 4400Hz 5000Hz 5400Hz Band Width 200Hz 3 band common Figure16 When there is no compensation of center frequency Setting of center frequency 4400Hz 5000Hz 5400Hz Band Width 200Hz 3 band common Fig...

Page 40: ...This dialog can easily set the AK4671 s 5 Band Equalizer Figure 18 5 Band EQ window When the check box of 5 Band EQ is checked 5 Band Equalizer is ON EQ bit 1 When the slide button is changed its valu...

Page 41: ...as critical componentsNote1 in any safety life support or other hazard related device or systemNote2 and AKEMD assumes no responsibility for such use except for the use approved with the express writ...

Page 42: ...7 8 9 10 11 12 13 14 15 16 17 18 19 20 CN4 80pin_4 CN4 80pin_4 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 TP51 PDN TP51 PDN 1 TP39 SDTI TP39 SDTI 1 R2 2 2k R2 2 2k TP65 SDTOA TP65 SD...

Page 43: ...SAIN_SEL JP28 SAIN_SEL JP19 HPR JACK JP19 HPR JACK R39 short R39 short JP30 GND JP30 GND JP29 TVDD3_SEL JP29 TVDD3_SEL JP58 L_16ohm JP58 L_16ohm JP27 TVDD2_SEL JP27 TVDD2_SEL C44 1u C44 1u R41 10 R41...

Page 44: ...2Y 4 3A 5 3Y 6 Vcc 14 GND 7 4Y 8 4A 9 5Y 10 5A 11 6Y 12 6A 13 U8 74HC14 U8 74HC14 1A 1 1Y 2 2A 3 2Y 4 3A 5 3Y 6 Vcc 14 GND 7 4Y 8 4A 9 5Y 10 5A 11 6Y 12 6A 13 JP36 MCLK JP36 MCLK U5 74AC163 U5 74AC163...

Page 45: ...C76 5p C73 0 1u C73 0 1u JP46 4114_MCKI JP46 4114_MCKI C77 0 1u C77 0 1u C78 0 1u C78 0 1u C72 10u C72 10u C71 0 1u C71 0 1u X2 11 2896MHz X2 11 2896MHz 1 2 OFF 1 2 3 4 5 6 S1 SW DIP 6 OFF 1 2 3 4 5...

Page 46: ...M S RP2 47k RP2 47k 7 6 5 4 3 2 1 C91 0 1u C91 0 1u R58 470 R58 470 R53 10k R53 10k JP64 BICKB JP64 BICKB C85 0 1u C85 0 1u PORT5 CTRL PORT5 CTRL 1 3 5 7 9 10 8 6 4 2 RP6 47k RP6 47k 7 6 5 4 3 2 1 U18...

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ASAHI AKD4671-B, Manual

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