[AKD4671-B]
<KM089001>
2008
/
03
-
15
-
(4) PLL Master Mode
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or
27MHz) is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The
MCKO output frequency is selected by PS1-0 bits and the output is enabled by MCKO bit. The BICK output
frequency is selected between 32fs or 64fs, by BCKO bit.
AK4671
DSP or
μ
P
MCKO
BICK
LRCK
SDTO
SDTI
BCLK
LRCK
SDTI
SDTO
MCKI
1fs
32fs, 64fs
256fs/128fs/64fs/32fs
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
MCLK
(4-1)
Evaluation of A/D using DIT of AK4114
J12 (EXT) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP).
X’tal oscillator should be removed from X2.
In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 19.
The jumper pins should be set as the following.
When a termination (51
Ω
) is unnecessary, please set JP39 (EXT) open.
JP36
MCLK
JP33
BICK_SEL
4040
DIR
DIR
EXT
JP38
LRCK_SEL
4040
DIR
JP39
EXT
JP46
4114_MCKI
JP35
PHASE
INV
THR
JP7
MCKO
JP48
M/S
Slave
Master
