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ASAHI AKD4671-B, Manual

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ASAHI AKD4671-B Manual Download Page 46

A

A

B

B

C

C

D

D

E

E

E

E

D

D

C

C

B

B

A

A

CAD0

DAUX

VCC

CDTI/SDA

D3V

4114_SDTO

CCLK/SCL

CSN/CAD0

D3V

D3V

VCC

VCC

EXT_BICKA

EXT_LRCKA

D3V

VCC2

EXT_BICKB

EXT_LRCKB

D3V

VCC2

EXT_MCLK2

SDTOA1

SDTIA

SDTIB

EXT_MCLK2

SDTOB1

D3V

4670_CDTO

D3V

I2C

4670_I2C

4670_BICKA

4670_SYNCA

4670_BICKB

4670_SYNCB

D3V

VCC2

4670_BICK

4670_LRCK

EXT_BICK

EXT_LRCK

4670_MCKO

4670_SDTO

MCKO

SDTIA

SDTIB

4670_SDTIA

4670_SDTIB

SDTOA1

SDTOB1

4670_SDTOA

4670_SDTOB

EXT_MCLK2

EXT_MCLK

4670_MCKI

4670_SDTI

Title

Size

Document Number

Rev

Date:

Sheet

of

LOGIC

1

AKD4671-B

A2

5

5

Wednesday, March 26, 2008

Title

Size

Document Number

Rev

Date:

Sheet

of

LOGIC

1

AKD4671-B

A2

5

5

Wednesday, March 26, 2008

Title

Size

Document Number

Rev

Date:

Sheet

of

LOGIC

1

AKD4671-B

A2

5

5

Wednesday, March 26, 2008

CCLK/SCI

CDTO/SDA(ACK)

CDTI/SDA

CSN

LRCK

MCLK

VCC

SDTI

BICK

4-WIRE

I2C (CAD0)

Slave

Mast

er

ADC

DIR

GND

GND

SDTO

BI

C

K

A

BI

C

K

B

LRCKA

MCLK2

VCC

SDTIA

BICKA

GND

GND

SDTOA

THR

INV

LRCKB

MCLK2

VCC

SDTIB

BICKB

GND

GND

SDTOB

THR

INV

I2C (ACK)

4-WIRE (CDTO)

SCLK

CSN

DIN

DOUT

VCCIO

MCLK2

I2C

U12

74AVC8T245

U12

74AVC8T245

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

10

B1

21

B2

20

B3

19

B4

18

B5

17

B6

16

B7

15

B8

14

GND

11

GND

12

GND

13

VCCA

1

DIR

2

VCCB

24

VCCB

23

OE

22

R61

1k

R61

1k

PORT4

DSP

PORT4

DSP

1
3
5
7
9

10

8

6

4

2

R56

10k

R56

10k

JP49

PLLBT

JP49

PLLBT

C89

0.1u

C89

0.1u

C86

0.1u

C86

0.1u

C88

0.1u

C88

0.1u

C90

0.1u

C90

0.1u

JP54

BICKB PHASE

JP54

BICKB PHASE

RP5 47k

RP5 47k

7
6
5
4
3
2
1

JP53

CTRL_SEL2

JP53

CTRL_SEL2

C93

0.1u

C93

0.1u

R54
10k

R54
10k

C82

0.1u

C82

0.1u

JP51

SDTI_SEL

JP51

SDTI_SEL

U15 74HC14

U15 74HC14

1A

1

1Y

2

2A

3

2Y

4

3A

5

3Y

6

Vcc

14

GND

7

4Y

8

4A

9

5Y

10

5A

11

6Y

12

6A

13

JP48

M/S

JP48

M/S

RP2 47k

RP2 47k

7
6
5
4
3
2
1

C91

0.1u

C91

0.1u

R58

470

R58

470

R53
10k

R53
10k

JP64

BICKB

JP64

BICKB

C85

0.1u

C85

0.1u

PORT5

CTRL

PORT5

CTRL

1

3

5

7

9

10

8
6
4
2

RP6 47k

RP6 47k

7
6
5
4
3
2
1

U18

74AVC4T245

U18

74AVC4T245

1A1

4

1A2

5

2A2

7

1OE

15

1B1

13

1B2

12

2B1

11

2B2

10

GND

9

2A1

6

1DIR

2

VCCB

16

VCCA

1

GND

8

2DIR

3

2OE

14

JP56

D3V

JP56

D3V

U16

74LVC07

U16

74LVC07

1A

1

2A

3

3A

5

4A

9

5A

11

6A

13

Vcc

14

GND

7

1Y

2

2Y

4

3Y

6

4Y

8

5Y

10

6Y

12

U13

74AVC8T245

U13

74AVC8T245

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

10

B1

21

B2

20

B3

19

B4

18

B5

17

B6

16

B7

15

B8

14

GND

11

GND

12

GND

13

VCCA

1

DIR

2

VCCB

24

VCCB

23

OE

22

C87

0.1u

C87

0.1u

JP47

BICKA PHASE

JP47

BICKA PHASE

U14

74AVC8T245

U14

74AVC8T245

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

10

B1

21

B2

20

B3

19

B4

18

B5

17

B6

16

B7

15

B8

14

GND

11

GND

12

GND

13

VCCA

1

DIR

2

VCCB

24

VCCB

23

OE

22

R59

470

R59

470

PORT7

CTRL SAR ADC

PORT7

CTRL SAR ADC

1

3

5

7

9

10

8
6
4
2

JP50

SDTOA LOOP

JP50

SDTOA LOOP

JP63

SYNCA

JP63

SYNCA

RP3 47k

RP3 47k

7
6
5
4
3
2
1

PORT6

Bluetooth

PORT6

Bluetooth

1
3
5
7
9

10

8

6

4

2

JP55

SDTOB LOOP

JP55

SDTOB LOOP

U17

74AVC8T245

U17

74AVC8T245

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

10

B1

21

B2

20

B3

19

B4

18

B5

17

B6

16

B7

15

B8

14

GND

11

GND

12

GND

13

VCCA

1

DIR

2

VCCB

24

VCCB

23

OE

22

C84

0.1u

C84

0.1u

RP4 47k

RP4 47k

7
6
5
4
3
2
1

R60

470

R60

470

JP52

CTRL_SEL

JP52

CTRL_SEL

U11

74AVC8T245

U11

74AVC8T245

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

10

B1

21

B2

20

B3

19

B4

18

B5

17

B6

16

B7

15

B8

14

GND

11

GND

12

GND

13

VCCA

1

DIR

2

VCCB

24

VCCB

23

OE

22

C95

0.1u

C95

0.1u

R55

10k

R55

10k

JP65

SYNCB

JP65

SYNCB

PORT3

Baseband

PORT3

Baseband

1
3
5
7
9

10

8

6

4

2

C92

0.1u

C92

0.1u

C83

0.1u

C83

0.1u

C94

0.1u

C94

0.1u

JP61

SDTIB

JP61

SDTIB

RP7 47k

RP7 47k

7
6
5
4
3
2
1

R57

10k

R57

10k

JP57

I2C PIN

JP57

I2C PIN

R62
10k

R62
10k

JP60

SDTIA

JP60

SDTIA

JP62

BICKA

JP62

BICKA

Summary of Contents for AKD4671-B

Page 1: ...software are packed with this This control software does not support Windows NT FUNCTION DIT DIR with optical input output 10pin Header for Digital Audio I F PCM I F Baseband Bluetooth BNC connector f...

Page 2: ...from ROUT pin J5 It is analog signal input Jack The signal is input to LIN2 or LIN3 or LIN4 pins and JP23 should be selected J7 It is analog signal input Jack The signal is input to RIN2 or RIN3 or R...

Page 3: ...T4 The clock and data of DSP can be inputted and outputted with this connector PORT6 The clock and data of Bluetooth mode can be inputted and outputted with this connector 7 PORT1 PORT2 Optical Connec...

Page 4: ...open 3 3V supplied PVDD Orange 2 2 3 6V PVDD for AK4671 Default open typ 3 3V open 3 3V supplied DVDD Orange 1 6 3 6V DVDD for AK4671 Default open typ 3 3V open 3 3V supplied TVDD2 Orange 1 6 3 6V TVD...

Page 5: ...3 3V TVDD2 Orange 1 6 3 6V TVDD2 for AK4671 Default should be connected typ 3 3V 3 3V TVDD3 Orange 1 6 3 6V TVDD3 for AK4671 Default should be connected typ 3 3V 3 3V VCC Orange 1 6 3 6V for logic De...

Page 6: ...s fed externally BICK and LRCK are divided with a board 1 5 All interface signals including master clock are fed externally 2 External Master Mode 2 1 Evaluation of A D using DIT of AK4114 2 2 Evaluat...

Page 7: ...1 DSP or P MCKI BICK LRCK SDTO SDTI BCLK LRCK SDTI SDTO MCKO 1fs 32fs MCLK 256fs 384fs 512fs 768fs or 1024fs 1 1 Evaluation of A D using DIT of AK4114 X2 X tal and PORT2 DIT are used Nothing should be...

Page 8: ...according to the frequency of MCLK BICK and LRCK Follows are setting examples in MCLK 256fs BICK 64fs and LRCK 1fs When MCLK 384fs or 768fs JP32 JP34 and JP37 should be set to 384 side 1 5 All interf...

Page 9: ...used Nothing should be connected to PORT1 DIR and PORT4 DSP In Master Mode BICK and LRCK of AK4671 should be input to AK4114 Please refer to Table 2 on page 19 The jumper pins should be set as the fol...

Page 10: ...2 4 All interface signals including master clock are fed externally PORT4 DSP is used Nothing should be connected to PORT1 DIR and PORT2 DIT The jumper pins should be set as the following JP36 MCLK DI...

Page 11: ...quency can be selected by FS3 0 bits 3 1 PLL Reference Clock MCKI pin AK4671 DSP or P MCKO BICK LRCK SDTO SDTI BCLK LRCK SDTI SDTO MCKI 1fs 32fs MCLK 256fs 128fs 64fs 32fs 11 2896MHz 12MHz 12 288MHz 1...

Page 12: ...en 3 1 3 All interface signals including master clock are fed externally PORT4 DSP is used Nothing should be connected to PORT1 DIR and PORT2 DIT The jumper pins should be set as the following JP36 MC...

Page 13: ...P MCKI BICK LRCK SDTO SDTI BCLK LRCK SDTI SDTO MCKO 1fs 32fs PLL Reference Clock LRCK pin 3 2 1 Evaluation of A D using DIT of AK4114 X2 X tal and PORT2 DIT are used Nothing should be connected to PO...

Page 14: ...master clock are fed externally PORT4 DSP is used Nothing should be connected to PORT1 DIR and PORT2 DIT The jumper pins should be set as the following JP36 MCLK JP33 BICK_SEL 4040 DIR DIR EXT JP38 LR...

Page 15: ...CK SDTI SDTO MCKI 1fs 32fs 64fs 256fs 128fs 64fs 32fs 11 2896MHz 12MHz 12 288MHz 13MHz 13 5MHz 19 2MHz 24MHz 26MHz 27MHz MCLK 4 1 Evaluation of A D using DIT of AK4114 J12 EXT and PORT2 DIT are used N...

Page 16: ...4 3 All interface signals including master clock are fed externally PORT4 DSP is used Nothing should be connected to PORT1 DIR and PORT2 DIT The jumper pins should be set as the following JP36 MCLK J...

Page 17: ...ut clock frequency of BICKA or BICKB pin AK4671 does not support master mode for both PCM I F A and B nor slave mode for both PCM I F A and B When PMPCM bit is 0 SYNCA BICKA SYNCB and BICKB pins are H...

Page 18: ...lock SYNCA or BICKA pin 1 1 SYNCA and BICKA are fed from on board clock generator X1 X tal PORT3 Baseband Module and PORT6 Bluetooth Module are used The jumper pins should be set as the following Plea...

Page 19: ...odule PORT3 Baseband Module and PORT6 Bluetooth Module are used SYNCA and BICKA should be supplied from PORT3 The jumper pins should be set as the following JP47 BICKA PHASE is jumper which decides po...

Page 20: ...lock SYNCB or BICKB pin 2 1 SYNCB and BICKB are fed from on board clock generator X1 X tal PORT3 Baseband Module and PORT6 Bluetooth Module are used The jumper pins should be set as the following Plea...

Page 21: ...h Module PORT3 Baseband Module and PORT6 Bluetooth Module are used Please supply SYNCB and BICKB from PORT6 The jumper pins should be set as the following JP54 BICKB PHASE is jumper which decides pola...

Page 22: ...eft justified 16bit Right justified H L O 64fs O 0 0 1 24bit Left justified 18bit Right justified H L O 64fs O 0 1 0 24bit Left justified 20bit Right justified H L O 64fs O 0 1 1 24bit Left justified...

Page 23: ...Default JP4 RIN1 RIN1 input GND In case of full differential input MPWR MIC power is supplied to RIN1 OPEN MIC power is not supplied to RIN1 Default JP7 MCKO MCKO output SHORT When AK4671 outputs MCK...

Page 24: ...lel port of IBM AT compatible PC Connect PORT5 CTRL with PC by 10 wire flat cable packed with the AKD4671 Table 4 shows switch and jumper settings for serial control I2C Mode should be selected in Tab...

Page 25: ..._SEL LIN2 RIN1 C50 1u R39 short 1 2 3 4 5 J5 LIN LIN1 LIN4 LIN3 Figure 4 LIN1 RIN1 LIN2 RIN2 LIN3 RIN3 and LIN4 RIN4 Input Circuit LIN2 RIN2 LIN3 RIN3 and LIN4 RIN4 share J5 J7 JP23 LIN_SEL and JP25 R...

Page 26: ...UT2 ROUT3 ROUT1 ROUT3 LOUT1 JP21 ROUT_SEL ROUT2 1 2 3 J3 HP ROUT1 R36 16 JP58 L_16ohm 1 2 3 4 5 J1 LOUT C47 100u R37 short JP59 R_16ohm JP17 HPL JACK JP16 LOUT_SEL JP19 HPR JACK Figure 6 LOUT1 ROUT1 L...

Page 27: ...am according to explanation above 2 Click Port Reset button 3 Click Write default button Explanation of each buttons Port Reset Set up the USB interface board AKDUSBIF A Write default Initialize the r...

Page 28: ...4671 click OK button If not click Cancel button 3 Function2 Dialog Dialog to evaluate DATT Address Box Input registers address in 2 figures of hexadecimal Start Data Box Input starts data in 2 figures...

Page 29: ...file name is akr Operation flow 1 Click Save Button 2 Set the file name and push Save Button The extension of file name is akr 4 2 Open The register setting data saved by Save is written to AK4671 Th...

Page 30: ...val time Set 1 to the address of the step where the sequence should be paused 3 Click Start button Then this sequence is executed The sequence is paused at the step of Interval 1 Click START button th...

Page 31: ...1 B KM089001 2008 03 31 6 Function4 Dialog The sequence that is created on Function3 can be assigned to buttons and executed When F4 button is clicked the window as shown in Figure 9 opens Figure 8 F4...

Page 32: ...cuted 6 2 SAVE and OPEN buttons on right side SAVE The sequence file names can assign be saved The file name is ak4 OPEN The sequence file names assign that are saved in ak4 are loaded 6 3 Note 1 This...

Page 33: ...ns and executed When F5 button is clicked the following window as shown in Figure 11 opens Figure 10 F5 window 7 1 OPEN buttons on left side and WRITE button 1 Click OPEN button and select the registe...

Page 34: ...n can be saved The file name is ak5 OPEN The register setting file names assign that are saved in ak5 are loaded 7 3 Note 1 All files need to be in same folder used by SAVE and OPEN function on right...

Page 35: ...easily set the AK4671 s programmable filter A calculation of a coefficient of Digital Programmable Filter such as HPF EQ filter a write to a register and check frequency response Window to show to Fig...

Page 36: ...e Frequency fs 10000 Pole Frequency 0 497 fs Zero point Frequency Zero point Frequency fs 10000 Zero point Frequency 0 497 fs Gain Gain 0dB Gain 12dB 5 Band Equalizer EQ1 5 Center Frequency EQ1 5 Cent...

Page 37: ...displayed and a calculation of register setting is not executed Figure14 A register setting calculation result In the following cases a register set values are updated 1 When Register Setting button w...

Page 38: ...n Notch Filter Auto Correction 8 4 Automatic compensation for center frequency of a notch filter When a gain of 5 band Equalizer is set to 1 Equalizer becomes a notch filter When center frequency of s...

Page 39: ...uency 4400Hz 5000Hz 5400Hz Band Width 200Hz 3 band common Figure16 When there is no compensation of center frequency Setting of center frequency 4400Hz 5000Hz 5400Hz Band Width 200Hz 3 band common Fig...

Page 40: ...This dialog can easily set the AK4671 s 5 Band Equalizer Figure 18 5 Band EQ window When the check box of 5 Band EQ is checked 5 Band Equalizer is ON EQ bit 1 When the slide button is changed its valu...

Page 41: ...as critical componentsNote1 in any safety life support or other hazard related device or systemNote2 and AKEMD assumes no responsibility for such use except for the use approved with the express writ...

Page 42: ...7 8 9 10 11 12 13 14 15 16 17 18 19 20 CN4 80pin_4 CN4 80pin_4 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 TP51 PDN TP51 PDN 1 TP39 SDTI TP39 SDTI 1 R2 2 2k R2 2 2k TP65 SDTOA TP65 SD...

Page 43: ...SAIN_SEL JP28 SAIN_SEL JP19 HPR JACK JP19 HPR JACK R39 short R39 short JP30 GND JP30 GND JP29 TVDD3_SEL JP29 TVDD3_SEL JP58 L_16ohm JP58 L_16ohm JP27 TVDD2_SEL JP27 TVDD2_SEL C44 1u C44 1u R41 10 R41...

Page 44: ...2Y 4 3A 5 3Y 6 Vcc 14 GND 7 4Y 8 4A 9 5Y 10 5A 11 6Y 12 6A 13 U8 74HC14 U8 74HC14 1A 1 1Y 2 2A 3 2Y 4 3A 5 3Y 6 Vcc 14 GND 7 4Y 8 4A 9 5Y 10 5A 11 6Y 12 6A 13 JP36 MCLK JP36 MCLK U5 74AC163 U5 74AC163...

Page 45: ...C76 5p C73 0 1u C73 0 1u JP46 4114_MCKI JP46 4114_MCKI C77 0 1u C77 0 1u C78 0 1u C78 0 1u C72 10u C72 10u C71 0 1u C71 0 1u X2 11 2896MHz X2 11 2896MHz 1 2 OFF 1 2 3 4 5 6 S1 SW DIP 6 OFF 1 2 3 4 5...

Page 46: ...M S RP2 47k RP2 47k 7 6 5 4 3 2 1 C91 0 1u C91 0 1u R58 470 R58 470 R53 10k R53 10k JP64 BICKB JP64 BICKB C85 0 1u C85 0 1u PORT5 CTRL PORT5 CTRL 1 3 5 7 9 10 8 6 4 2 RP6 47k RP6 47k 7 6 5 4 3 2 1 U18...

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