[AKD4671-B]
<KM089001>
2008
/
03
-
17
-
2. PCM I/F evaluation mode
A reference clock of PLLBT is selected among the input clocks to SYNCA, BICKA, SYNCB or BICKB pin.
The required clock to PCM I/F is generated by an internal PLLBT circuit. PLLBT circuit is powered up by
PMPCM bit. Input frequency is selected by PLLBT2-0 bits. BCKO2 bit select the output clock frequency of
BICKA or BICKB pin.
AK4671 does not support master mode for both PCM I/F A and B nor slave mode
for both PCM I/F A and B. When PMPCM bit is “0”, SYNCA, BICKA, SYNCB and BICKB pins are Hi-Z.
(1) PLLBT reference clock: SYNCA or BICKA pin
(1-1)
SYNCA and BICKA are fed from on-board clock generator.
(1-2) SYNCA and BICKA are fed externally via PORT3 (Baseband Module).
(2) PLLBT reference clock: SYNCB or BICKB pin
(2-1)
SYNCB and BICKB are fed from on-board clock generator.
(2-2) SYNCB and BICKB are fed externally via PORT6 (Bluetooth Module).
