[AKD4671-B]
<KM089001>
2008
/
03
-
7
-
(1) External Slave Mode
When PMPLL bit is “0”, the AK4671 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL
circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to
operate are MCKI (256fs, 384fs, 512fs, 768fs or 1024fs), LRCK (fs) and BICK (
≥
32fs). The master clock (MCKI)
should be synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI
is selected by FS1-0 bits.
AK4671
DSP or
μ
P
MCKI
BICK
LRCK
SDTO
SDTI
BCLK
LRCK
SDTI
SDTO
MCKO
1fs
≥
32fs
MCLK
256fs, 384fs, 512fs,
768fs or 1024fs
(1-1)
Evaluation of A/D using DIT of AK4114
X2 (X’tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP).
The jumper pins should be set as the following.
(1-2) Evaluation of D/A using DIR of AK4114
PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT4 (DSP).
The jumper pins should be set as the following.
JP36
MCLK
DIR
EXT
JP35
PHASE
INV
THR
JP38
LRCK_SEL
4040
DIR
4040
DIR
JP33
BICK_SEL
JP46
4114_MCKI
JP48
M/S
Slave
Master
JP36
MCLK
DIR
EXT
JP35
PHASE
INV
THR
JP38
LRCK_SEL
4040
DIR
JP51
SDTI_SEL
ADC
DIR
JP33
BICK_SEL
4040
DIR
JP48
M/S
Slave
Master
