[AKD4671-B]
<KM089001>
2008
/
03
-
11
-
(3) PLL Slave Mode
A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to
the AK4671 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits.
BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose
not matter. MCKO pin outputs the frequency selected by PS1-0 bits and the output is enabled by MCKO bit.
Sampling frequency can be selected by FS3-0 bits.
(3-1) PLL Reference Clock : MCKI pin
AK4671
DSP or
μ
P
MCKO
BICK
LRCK
SDTO
SDTI
BCLK
LRCK
SDTI
SDTO
MCKI
1fs
≥
32fs
MCLK
256fs/128fs/64fs/32fs
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
(3-1-1) Evaluation of A/D using DIT of AK4114
J12 (EXT) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP).
X’tal oscillator should be removed from X2.
The jumper pins should be set as the following.
When a termination (51
Ω
) is unnecessary, please set JP39 (EXT) to open.
JP36
MCLK
JP33
BICK_SEL
4040
DIR
DIR
EXT
JP38
LRCK_SEL
4040
DIR
JP39
EXT
JP46
4114_MCKI
JP35
PHASE
INV
THR
JP7
MCKO
JP48
M/S
Slave
Master
