[AKD4671-B]
<KM089001>
2008
/
03
-
8
-
(1-3) Evaluation of Loop-back using AK4114 <default>
X2 (X’tal) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP).
The jumper pins should be set as the following.
(1-4) Evaluation of Loop-back where master clock is fed externally, BICK and LRCK are generated by
on-board
divider.
J12 (EXT) is used . MCLK is supplied from J12 (EXT). BICK and LRCK are generated by 74HC4040 on
AKD4671-B.
Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP).
The jumper pins should be set as the following.
When a termination (51
Ω
) is unnecessary, please set JP39 (EXT) open.
JP32 (MKFS), JP34 (BCFS), and JP37 (LRCK) should be set according to the frequency of MCLK, BICK and
LRCK.
Follows are setting examples in MCLK=256fs , BICK=64fs and LRCK=1fs.
When MCLK=384fs or 768fs, JP32, JP34, and JP37 should be set to “384” side.
.
(1-5) All interface signals including master clock are fed externally
PORT4 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT).
The jumper pins should be set as the following.
JP36
MCLK
DIR
EXT
JP35
PHASE
INV
THR
JP38
LRCK_SEL
4040
DIR
JP51
SDTI_SEL
ADC
DIR
JP33
BICK_SEL
4040
DIR
JP46
4114_MCKI
JP48
M/S
Slave
Master
JP36
MCLK
JP33
BICK_SEL
4040
DIR
DIR
EXT
JP38
LRCK_SEL
4040
DIR
JP51
SDTI_SEL
ADC
DIR
JP39
EXT
JP48
M/S
Slave
Master
JP34
BCFS
JP32
MKFS
256fs
512fs
1024fs
384/768fs
MCKO
64fs-384
32fs-384
64fs
32fs
JP37
LRCK
fs-384
fs
JP36
MCLK
JP33
BICK_SEL
4040
DIR
DIR
EXT
JP38
LRCK_SEL
4040
DIR
JP51
SDTI_SEL
ADC
DIR
JP48
M/S
Slave
Maste
