ARM ARM9TDMI, Technical Reference Manual

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Debug Support
5-42 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B
If bit 3 of the control register is programmed to 0, the comparators will examine the
instruction address, instruction data and instruction control buses. In this case bits [1:0]
of the mask register must be set to “don’t care” (programmed to 11). The format of the
register in this case is as shown in Figure 5-11.
Figure 5-11 Watchpoint control register for instruction comparison
CHAIN Can be connected to chain output of another watchpoint in order to
implement, for example, debugger requests of the form “breakpoint on
address YYY only when in process XXX”.
In the ARM9TDMI EmbeddedICE macrocell, the CHAINOUT output of
watchpoint 1 is connected to the CHAIN input of watchpoint 0. The
CHAINOUT output is derived from a latch. The address/control field
comparator drives the write enable for the latch and the input to the latch is
the value of the data field comparator. The
CHAINOUT latch is cleared when
the control value register is written or when nTRST is LOW.
RANGE Can be connected to the range output of another watchpoint register. In the
ARM9TDMI EmbeddedICE macrocell, the
RANGEOUT output of
watchpoint 1 is connected to the RANGE input of watchpoint 0. This allows
two watchpoints to be coupled for detecting conditions that occur
simultaneously, for example, for range-checking.
ENABLE If a watchpoint match occurs, the internal Watchpoint signal will only be
asserted when the ENABLE bit is set. This bit only exists in the value register,
it cannot be masked.
Table 5-5 Watchpoint control register for data comparison bit functions
Bit Function
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