ARM ARM9TDMI, Technical Reference Manual

Page: 41 / 154

ARM9TDMI Coprocessor Interface
ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. 4-5
As with all other instructions, the ARM9TDMI processor core performs the main
decode off the rising edge of the clock during the decode stage. From this, the core
commits to executing the instruction, and so performs an instruction fetch. The
coprocessor instruction pipeline keeps in step with the ARM9TDMI by monitoring
InMREQ .
At the falling edge of GCLK , if nWAIT is HIGH, and InMREQ is LOW, an instruction
fetch is taking place, and ID[31:0] will contain the fetched instruction on the next
falling edge of the clock, when nWAIT is HIGH. This means that:
• the last instruction fetched should enter the decode stage of the coprocessor
pipeline
• the instruction in the decode stage of the coprocessor pipeline should enter its
execute stage
• the fetched instruction should be latched.
In all other cases, the ARM9TDMI pipeline is stalled, and the coprocessor pipeline
should not advance.
Figure 4-2 shows the timing for these signals, and indicates when the coprocessor
pipeline should advance its state. In this timing diagram, Coproc Clock shows a
processed version of
GCLK with InMREQ and nWAIT . This is one method of
generating a clock to reflect the advance of the ARM9TDMI pipeline.
Figure 4-2 ARM9TDMI coprocessor clocking
During the execute stage, the condition codes are combined with the flags to determine
whether the instruction really executes or not. The output
PASS is asserted (HIGH) if
the instruction in the execute stage of the coprocessor pipeline:
• is a coprocessor instruction
• has passed its condition codes.
—
˜™›˜Œ
•˜Œ”