ARM9TDMI Processor Core Memory Interface
3-2
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM DDI0145B
3.1
About the memory interface
The ARM9TDMI has a Harvard bus architecture with separate instruction and data
interfaces. This allows concurrent instruction and data accesses, and greatly reduces the
CPI of the processor. For optimal performance, single cycle memory accesses for both
interfaces are required, although the core can be wait-stated for non-sequential accesses,
or slower memory systems.
For both instruction and data interfaces, the ARM9TDMI process core uses pipelined
addressing. The address and control signals are generated the cycle before the data
transfer takes place, giving any decode logic as much advance notice as possible. All
memory accesses are generated from
GCLK
.
For each interface there are different types of memory access:
•
non-sequential
•
sequential
•
internal
•
coprocessor transfer (for the data interface).
These accesses are determined by
InMREQ
and
ISEQ
for the instruction interface, and
by
DnMREQ
and
DSEQ
for the data interface.
The ARM9TDMI can operate in both big-endian and little-endian memory
configurations, and this is selected by the
BIGEND
input. The endian configuration
affects both interfaces, so care must be taken in designing the memory interface logic
to allow correct operation of the processor core.
For system purposes, it is normally necessary to provide some mechanism whereby the
data interface can access instruction memory. There are two main reasons for this:
•
The use of in-line data for literal pools is very common. This data will be fetched
via the data interface but will normally be contained in the instruction memory
space.
•
To enable debug via the JTAG interface it must be possible to download code into
the instruction memory. This code has to be written to memory via the data data
bus as the instruction data bus is unidirectional. This means in this instance it is
essential for the data interface to have access to the instruction memory.
A typical implementation of an ARM9TDMI-based cached processor has Harvard
caches and a unified memory structure beyond the caches, thereby giving the data
interface access to the instruction memory space. The ARM940T is an example of such
a system. However, for an SRAM-based system this technique cannot be used, and an
alternative method must be employed.
Summary of Contents for ARM9TDMI
Page 6: ...Contents vi Copyright 1998 1999 ARM Limited All rights reserved ARM DDI0145B ...
Page 12: ...Preface xii Copyright 1998 1999 ARM Limited All rights reserved ARM DDI0145B ...
Page 16: ...Introduction 1 4 Copyright 1998 1999 ARM Limited All rights reserved ARM DDI0145B ...
Page 22: ...Programmer s Model 2 6 Copyright 1998 1999 ARM Limited All rights reserved ARM DDI0145B ...
Page 110: ...Test Issues 6 6 Copyright 1998 1999 ARM Limited All rights reserved ARM DDI0145B ...
Page 154: ...Index Index 4 Copyright 1998 1999 ARM Limited All rights reserved ARM DDI0145B ...
