ARM ARM9TDMI, Technical Reference Manual

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ARM9TDMI Processor Core Memory Interface
3-4 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B
3.2 Instruction interface
Whenever an instruction enters the execute stage of the pipeline, a new opcode is
fetched from the instruction bus. The ARM9TDMI processor core may be connected to
a variety of cache/SRAM systems, and it is optimized for single cycle access systems.
However, in order to ease the system design, it is possible to connect the ARM9TDMI
to memory which takes two (or more) cycles for a
non-sequential (N) access, and one
cycle for a sequential (S) access. Although this increases the effective CPI, it
considerably eases the memory design.
The ARM9TDMI indicates that an instruction fetch will take place by driving
InMREQ LOW. The instruction address bus, IA[31:1] will contain the address for the
fetch, and the ISEQ signal will indicate whether the fetch is sequential or
non-sequential to the previous access. All these signals become valid towards the end
of phase 2 of the cycle that precedes the instruction fetch.
The timing is shown in Figure 3-2 on page 3-5. The full encoding of InMREQ and
ISEQ is as follows:
Note
The 1,1 case does not occur in this implementation but may be used in the future.
Instruction fetches may be marked as aborted. The IABORT signal is an input to the
processor with the same timing as the instruction data. If, and when, the instruction
reaches the execute stage of the pipeline, the prefetch abort vector is taken. The timing
for this is shown in Figure 3-2 on page 3-5. If the memory control logic does not make
use of the
IABORT signal, it must be tied LOW.
Internal cycles occur when the processor is stalled, either waiting for an interlock to
resolve, or completing a multi-cycle instruction.
Table 3-1 InMREQ and ISEQ encoding
InMREQ ISEQ Cycle type
0 0 Non-sequential
0 1 Sequential
1 0 Internal
1 1 Reserved for future use