Appendix C. Reference
The STEbus and the TARGET386EX
STEbus is a high reliability 8 bit backplane system, ideal for
industrial I/O applications with powerful facilities for multi-
processing and interrupt handling.
STEbus boards are classified as either bus masters or slaves. A bus
master can initiate a bus transfer whereas a slave can only respond.
Generally bus masters are CPU boards which access memory and
I/O peripheral slave boards. Some slave boards do have on-board
microprocessors.
STEbus can support up to three bus masters in a system. One of
these is the default master, the other two are potential masters. The
default master contains a bus arbiter that controls which master
board has control on a transfer-by-transfer basis. Potential masters
request control of the bus from the bus master on BUSRQ0* or
BUSRQ1*. The arbiter grants bus control to one of the requesting
boards on a priority basis, BUSRQ0* has highest priority and
BUSRQ1* has lower priority, with BUSACK0* and BUSACK1*
signals respectively. Lowest priority is the default master which has
control of the bus when no other master requires it.
STEbus master and slave boards may be placed in any slot in the
STEbus backplane.
The TARGET386EX can act as either an STEbus master or slave. It
may also be used in multi-master systems. The STEbus mode is
controlled by on-board General Control Register 1. In default master
mode the board has an on-board bus arbiter enabled. Bus arbitration
is entirely transparent to any software running on any of the
masters. In bus requester mode the on-board arbiter is disabled and
another board must contain the arbiter. In slave mode the arbiter is
disabled and the TARGET386EX can make no STEbus accesses. Bus
masters may talk to the TARGET386EX in slave mode via the dual
port RAM which is only enabled in slave mode.
Only one board in an STEbus system should drive the 16MHz
SYSCLK signal.
STEbus slaves are accessed simply by memory and I/O read and
write commands from the master processor. These generate address
strobe (ADRSTB*), data strobe (DATSTB*), command modifier
(CM2 to CM0), address and data signals to the STEbus. Slave boards
that decode their address for a transfer respond with a DATACK*
signal when they have accepted or placed data on the STEbus. Slave
boards should be configured to fit in the STEbus memory or I/O
space available on the TARGET386EX. Note that if an STEbus slave
has a non-movable address then the memory and I/O maps on the
TARGET386EX are very flexible and may be re-configured using
2192-08270-000-000
Appendix C. Reference
J539 TARGET386EX
Page 35
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