LEDs
The C library routines supplied with the TARGET386EX fully
support the configuration of and access to these peripherals. Intels
ApBUILDER software, also supplied with the board, allow the user
to set up and access the ports at a lower software level.
Interrupt Assignments
Interrupts from STEbus, PC/104 and on-board peripherals are
routed to the 386EX INT7-0 lines via links for ease of configuration.
The link arrangement is shown below.
STEbus interrupts are level triggered, 386EX on-board peripherals
use edge triggered interrupts. The NOR gates shown in the
interrupt connection diagram shown above allow true level
triggered interrupts to be used on the STEbus. This is best illustrated
with an example. An STEbus board asserts ATNRQ2* low which
generates a low-high transition on interrupt to the CPU on INT2.
The software interrupt handler must know which ATNRQ* line was
asserted. On entering the interrupt handler the software writes a 1 to
bit 2 of the STEbus Control Register to disable the NOR gate
associated with ATNRQ2*. This causes the INT line to go low. The
interrupt handler then acts to clear the source of ATNRQ2*. At the
end of the interrupt handler the software writes a 0 to bit 2 of the
STEbus Control Register 0 and re-enables the NOR gate. If there was
only one source of ATNRQ2* then the INT2 line stays low and no
further interrupt is generated. If there are multiple sources of
ATNRQ2* and the line remains low after one source has been
2192-08270-000-000
Section 4. Using the TARGET386EX
J539 TARGET386EX
Page 23
Reference
D2 (RED)
D£ (GREEN)
386EX Parallel Port Connection
Port P3 bit 1
Port P3 bit 0
ATNRQ0*
ATNRQ1*
ATNRQ2*
ATNRQ3*
/EN0
/EN1
/EN2
/EN3
PC_IRQ10
PC_IRQ11
PC_IRQ12
PC_IRQ14
INT0
INT1
INT2
INT3
INT4
INT6
INT7
INT5
PC_IRQ5
PC_IRQ7
PC_IRQ6
PC_IRQ15
MAILBOX_INT
TFRERR_IN/BTO
INT_OUT
ATNRQ3*
ATNRQ2*
ATNRQ1*
ATNRQ0*
A
B
A
B
A
B
A
B
A
B
A
B
A
D
LK10
LK11
LK12
LK13
LK14
LK15
LK6
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