Section 4. Using the TARGET386EX
Programmable Memory and I/O Map
The TARGET386EX has a very flexible scheme for locating its on-
board memory, peripherals and expansion busses in its memory and
I/O maps. The 386EX processor has eight outputs called
programmable chip selects, namely UCS and CS0 to CS6. These
outputs may be programmed so that they become active over a
range of memory or I/O addresses and can be used to activate
devices connected to the 386EX. The table below shows how the chip
selects are used on the TARGET386EX with the default address
ranges programmed by the monitor after initialisation.
Chip selects CS0, CS1, CS2 and UCS are activated for the address
ranges indicated in the table to control CPU accesses to the on-board
memory and peripherals.
Any CPU access to an address that is not covered by one of CS0,
CS1, CS2 or UCS is automatically directed to the default expansion
bus. On power-up or reset the default expansion bus is the PC/104
interface. STEbus board variants can access peripheral boards on
both PC/104 and STEbus. On power-up or reset the STEbus is the
non-default expansion bus. As shown in the table above, 386EX chip
selects CS3, CS4, CS5 and CS6 can be used to direct CPU accesses
that would normally go to the default expansion bus to access the
non-default expansion bus instead.
This example illustrates the use of CS3 to CS6. The monitor software
sets the TARGET386EX up so that the memory area from 48000h to
7FFFFh is directed to the PC/104 bus by default. The user has an
STEbus memory board that exists in the memory address range
60000h to 6FFFFh. Any one of CS3 to CS6 may be programmed to
cover 60000h to 6FFFFh and CPU accesses to any address in this
range will then be diverted to the STEbus instead of the PC/104.
2192-08270-000-000
Section 4. Using the TARGET386EX
J539 TARGET386EX
Page 17
386EX
Chip Select
UCS
CS6
CS5
CS4
CS3
CS2
CS1
CS0
CS0
TARGET386EX Chip Select Use
Flash ROM
Accesses non-default expansion bus
Accesses non-default expansion bus
Accesses non-default expansion bus
Accesses non-default expansion bus
SVIF1 port, STEbus interrupt control
Register, General Control Registers 0
and 1
Dual port RAM (32KB)
NOT FITTED ON SBC VARIANTS
Main RAM (256KB)
Main RAM (512K)
Default Address Range
not programmed or enabled
not programmed or enabled
not programmed or enabled
not programmed or enabled
not programmed or enabled
FC00h-FFFFh, I/O
40000h - 47FFFh, MEMORY
not enabled if 512K main RAM
0 - 3FFFFh, MEMORY
0 - 7FFFF, MEMORY
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