2192-08270-000-000
Note: If 512K of RAM is enabled, then there can be no access to the
PC/104 or SETbus, as there is no room for this in the memory map,
as follows.
CS3, CS4, CS5 and CS6 can be programmed very flexibly to create
multiple holes in the default bus memory or I/O space that are
directed to the non-default bus.
The default expansion bus can be changed by writing to bit 2 of
General Control Register 1. If this bit is set to 1 then the STEbus
becomes the default expansion bus. CPU accesses not covered by
CS0, CS1, CS2 or UCS will then be automatically diverted to STEbus.
CPU accesses can then be diverted to the PC/104 bus by
programming CS3 to CS6 for the appropriate address ranges.
The Board Software Library supplied with the Development Kit
fully supports programming all the 386EX chip selects.
Note: On SBC board variants PC/104 is the only available expansion bus.
Programming the chip selects that control accesses to on-board Flash
ROM, memory and I/O can also be used to move these on-board
peripherals around in the address map, see Appendix B. Reference
for more details.
Memory Map
J539 TARGET386EX
Section 4. Using the TARGET386EX
Page 18
16KB Monitor after reset
(UCS)
Top of PC/104 memory space
16KB Monitor (UCS) after initialisation
PC/104 (default)
STEbus (CS3-6)
32KB Dual Port SRAM (CS1)
256KB SRAM (CS0)
Max. Flash ROM (UCS)
3FFFFFFh
3FFC00h
1000000h
100000h
FFFFFh
FC000h
FBFFFh
80000h
7FFFFh
48000h
40000h
3FFFFh
00000h
ROM
RAM
or 512K
RAM
1M
512K
0
The address range if the ROM or RAM can
be changed to make a hole in the memory
map for access to the external busses.
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