On-Board Control Registers
SVIF1 Port Registers
The SVIF1 port takes up 4 bytes of I/O space.
The default base address of the SVIF1 port under the monitor
software is I/O FC0Ch.
STEbus Interrupt Control Register [NOT SBC VARIANTS]
This register controls the NOR gates that pass the STEbus ATNRQx*
signals to 386EX INT0-3 inputs.
The default address of this register under the monitor software is
I/O FC00h. It is repeated at FC01h.
Signal description:
General Control Register 0 [NOT SBC VARIANTS]
This register is used to generate interrupts out onto the STEbus with
the board in STEbus slave mode and clear the STEbus DPR mailbox
interrupt.
The default address of this register under the monitor is I/O FC04h.
It is repeated at FC05h.
Signal description:
2192-08270-000-000
Section 4. Using the TARGET386EX
J539 TARGET386EX
Page 21
A1
1
1
0
1
0
Channel A Data
Channel B Data
Channel A Control
Channel B Control
1
0
0
A0
Function
Bit 7
Unused bits
6
5
4
3
S_INT3
2
S_INT2
1
S_INT1
0
S_INT0
Bit 7
Unused bits
6
5
4
3
Unused
2
INTOUT
1
BTOCLR
0
MBXCLR
Signal
S_INT3
S_INT2
S_INT1
S_INT0
Reset State
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Enables (0) and disables (1) ATNRQ3* (see
interrupts through to INT3. Set/reset by interrupt
service routine.
Enables (0) and disables (1) ATNRQ2*. See S_INT3
Enables (0) and disables (1) ATNRQ1*. See S_INT3
Enables (0) and disables (1) ATNRQ0*. See S_INT3
Signal
INTOUT
BTOCLR
S_INT1
Reset State
0
0
0
R/W
W
W
W
Description
Writing 1 to this bit generates an interrupt out
onto the STEbus in slave mode. This bit is reset by
an STEbus access to the DPR mailbox area.
Writing 1 clears the STEbus bus timeout/TFRERR interrupt
Writing 1 to this bit clears the STEbus DPR mailbox interrupt
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