Section 3. Links and Options
IMPORTANT NOTE
:
STEbus variants of the TARGET386EX board are shipped in, and
power-up in, STEbus slave mode. This means that it cannot yet
access other STEbus peripheral boards. To access STEbus peripheral
boards via the monitor, links LK2 and LK3 should be fitted to drive
STEbus SYSRST* and SYSCLK* signals and General Control Register
1 (default I/O location FC06h) should be written with 07h. This sets
the board up as a default STEbus master with any memory or I/O
accesses not allocated to on-board memory or peripherals being
routed to the STEbus. See following sections and appendices for
more details of board set-up.
Default Link Positions
Note: A + next to a link position indicates the default shipping position.
LK1. STEbus timeout to TFRERR* [STEbus VARIANTS ONLY]
If an STEbus transfer initiated by the TARGET386EX is not
completed within a set time (see LK8) then a bus timeout will occur
to terminate the cycle. This may be used to generate an interrupt
(see LK15) and LK1 allows a timeout to assert the STEbus TFRERR*
signal to notify other boards in the system that there has been a
transfer problem. DO NOT FIT THIS LINK if there is an Arcom
SCIMX or SCIM386SXplus board in the system as these boards have
TFRERR* linked directly to their processor NMI line.
2192-08270-000-000
Section 3. Links and Options
J539 TARGET386EX
Page 11
A B
LK18
LK16
LK12
LK13
LK11
LK7
LK19
LK17
LK15
LK14
LK10
A
B
C
D
E
F
LK5
LK6
LK4
A
B
C
D
LK1
A
LK2
B
LK3
LK8
A
B
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